Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg
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Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
97.78 97.78 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_hw_reset_cg_inst 97.78 1 100 1 64 64




Group Instance : adc_ctrl_hw_reset_cg_inst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.78 1 100 1 64 64




Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 1 44 97.78


Variables for Group Instance adc_ctrl_hw_reset_cg_inst
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
fsm_state_cp 17 1 16 94.12 100 1 1 0
lp_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
lp_sample_cnt_pow_cp 8 0 8 100.00 100 1 1 0
np_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
np_sample_cnt_pow_cp 16 0 16 100.00 100 1 1 0


Summary for Variable fsm_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 17 1 16 94.12


Automatically Generated Bins for fsm_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[NP_DONE] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[PWRDN] 2250 1 T5 10 T12 10 T55 2
auto[PWRUP] 131 1 T5 1 T12 1 T47 1
auto[ONEST_0] 87 1 T5 2 T47 1 T53 2
auto[ONEST_021] 15 1 T48 1 T53 1 T51 1
auto[ONEST_1] 86 1 T47 1 T48 1 T200 2
auto[ONEST_DONE] 5 1 T337 1 T338 1 T339 1
auto[LP_0] 122 1 T5 1 T12 1 T14 1
auto[LP_021] 29 1 T51 1 T203 1 T54 1
auto[LP_1] 143 1 T5 3 T12 1 T14 2
auto[LP_EVAL] 71 1 T47 1 T48 2 T53 1
auto[LP_SLP] 536 1 T5 2 T12 6 T47 3
auto[LP_PWRUP] 24 1 T51 1 T52 2 T89 1
auto[NP_0] 235 1 T5 2 T12 2 T14 1
auto[NP_021] 46 1 T49 1 T36 1 T15 1
auto[NP_1] 259 1 T5 1 T12 3 T14 1
auto[NP_EVAL] 23 1 T203 1 T15 1 T39 1



Summary for Variable lp_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lp_sample_cnt_min_max_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
max 5 1 T53 1 T237 1 T340 1
min 1970 1 T5 5 T12 9 T55 2



Summary for Variable lp_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for lp_sample_cnt_pow_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
pow[0x0] 1981 1 T5 5 T12 9 T55 2
pow[0x1] 4 1 T211 1 T202 1 T311 1
pow[0x2] 18 1 T41 1 T210 1 T18 3
pow[0x3] 36 1 T48 2 T286 1 T52 1
pow[0x4] 64 1 T47 1 T48 1 T53 1
pow[0x5] 110 1 T12 2 T48 3 T49 2
pow[0x6] 278 1 T5 3 T12 3 T47 3
pow[0x7] 548 1 T5 5 T12 8 T47 3



Summary for Variable np_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for np_sample_cnt_min_max_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
max 177 1 T5 2 T47 2 T48 3
min 1329 1 T5 4 T12 5 T55 2



Summary for Variable np_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 16 0 16 100.00


User Defined Bins for np_sample_cnt_pow_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
pow[0x0] 1336 1 T5 4 T12 5 T55 2
pow[0x1] 8 1 T38 2 T20 1 T341 2
pow[0x2] 49 1 T16 1 T40 2 T41 7
pow[0x3] 36 1 T35 1 T36 1 T39 1
pow[0x4] 65 1 T36 2 T15 2 T38 1
pow[0x5] 1 1 T342 1 - - - -
pow[0x6] 1 1 T48 1 - - - -
pow[0x7] 2 1 T211 1 T343 1 - -
pow[0x8] 3 1 T203 1 T342 1 T344 1
pow[0x9] 7 1 T200 1 T89 1 T345 2
pow[0xa] 14 1 T206 1 T346 1 T347 1
pow[0xb] 45 1 T53 1 T51 1 T15 1
pow[0xc] 67 1 T5 3 T12 1 T47 1
pow[0xd] 154 1 T5 1 T12 2 T48 2
pow[0xe] 303 1 T5 1 T12 2 T47 4
pow[0xf] 576 1 T5 5 T12 6 T47 3

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