Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2453	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2778	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2340	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2440	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2440	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2229	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2424	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2618	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2405	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2615	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2451	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2670	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2564	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2668	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2460	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2575	0	0
adc_en_ctl_rd_A	2147483647	1991	0	0
adc_fsm_rst_rd_A	2147483647	1699	0	0
adc_intr_ctl_rd_A	2147483647	2325	0	0
adc_lp_sample_ctl_rd_A	2147483647	1946	0	0
adc_pd_ctl_rd_A	2147483647	2214	0	0
adc_sample_ctl_rd_A	2147483647	1678	0	0
adc_wakeup_ctl_rd_A	2147483647	1813	0	0
intr_enable_rd_A	2147483647	2216	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2453	0	0
T14	253843	32	0	0
T15	0	9	0	0
T16	0	29	0	0
T17	0	41	0	0
T18	0	11	0	0
T19	0	17	0	0
T20	0	21	0	0
T21	0	26	0	0
T22	0	20	0	0
T23	0	15	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2778	0	0
T14	253843	20	0	0
T15	0	16	0	0
T16	0	40	0	0
T17	0	36	0	0
T18	0	9	0	0
T19	0	24	0	0
T20	0	12	0	0
T21	0	16	0	0
T22	0	24	0	0
T23	0	15	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2340	0	0
T14	253843	14	0	0
T15	0	7	0	0
T16	0	23	0	0
T17	0	34	0	0
T18	0	6	0	0
T19	0	9	0	0
T20	0	20	0	0
T21	0	15	0	0
T22	0	20	0	0
T23	0	24	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440	0	0
T14	253843	14	0	0
T16	0	31	0	0
T17	0	25	0	0
T18	0	11	0	0
T19	0	32	0	0
T20	0	20	0	0
T21	0	18	0	0
T22	0	34	0	0
T23	0	2	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0
T33	0	23	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440	0	0
T14	253843	11	0	0
T15	0	9	0	0
T16	0	35	0	0
T17	0	21	0	0
T18	0	20	0	0
T19	0	23	0	0
T20	0	9	0	0
T21	0	21	0	0
T22	0	25	0	0
T23	0	10	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2229	0	0
T14	253843	16	0	0
T15	0	4	0	0
T16	0	26	0	0
T17	0	28	0	0
T18	0	9	0	0
T19	0	12	0	0
T20	0	10	0	0
T21	0	17	0	0
T22	0	19	0	0
T23	0	9	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2424	0	0
T14	253843	17	0	0
T15	0	11	0	0
T16	0	12	0	0
T17	0	41	0	0
T18	0	7	0	0
T19	0	20	0	0
T20	0	15	0	0
T21	0	8	0	0
T22	0	20	0	0
T23	0	4	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2618	0	0
T14	253843	30	0	0
T15	0	27	0	0
T16	0	21	0	0
T17	0	37	0	0
T18	0	17	0	0
T19	0	24	0	0
T20	0	13	0	0
T21	0	21	0	0
T22	0	18	0	0
T23	0	11	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2405	0	0
T14	253843	22	0	0
T15	0	9	0	0
T16	0	15	0	0
T17	0	28	0	0
T18	0	15	0	0
T19	0	21	0	0
T20	0	16	0	0
T21	0	1	0	0
T22	0	22	0	0
T23	0	6	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2615	0	0
T14	253843	31	0	0
T15	0	8	0	0
T16	0	32	0	0
T17	0	38	0	0
T18	0	17	0	0
T19	0	33	0	0
T20	0	21	0	0
T21	0	20	0	0
T22	0	18	0	0
T23	0	12	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2451	0	0
T14	253843	26	0	0
T15	0	4	0	0
T16	0	23	0	0
T17	0	34	0	0
T18	0	12	0	0
T19	0	16	0	0
T20	0	23	0	0
T21	0	22	0	0
T22	0	15	0	0
T23	0	8	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2670	0	0
T14	253843	18	0	0
T15	0	7	0	0
T16	0	21	0	0
T17	0	34	0	0
T18	0	16	0	0
T19	0	9	0	0
T20	0	28	0	0
T21	0	12	0	0
T22	0	32	0	0
T23	0	9	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2564	0	0
T14	253843	13	0	0
T15	0	4	0	0
T16	0	32	0	0
T17	0	43	0	0
T18	0	13	0	0
T19	0	6	0	0
T20	0	12	0	0
T21	0	22	0	0
T22	0	22	0	0
T23	0	10	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2668	0	0
T14	253843	17	0	0
T15	0	6	0	0
T16	0	14	0	0
T17	0	22	0	0
T18	0	11	0	0
T19	0	31	0	0
T20	0	28	0	0
T21	0	29	0	0
T22	0	18	0	0
T23	0	25	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2460	0	0
T14	253843	30	0	0
T15	0	3	0	0
T16	0	46	0	0
T17	0	28	0	0
T18	0	20	0	0
T19	0	6	0	0
T20	0	10	0	0
T21	0	8	0	0
T22	0	21	0	0
T23	0	8	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2575	0	0
T14	253843	28	0	0
T15	0	21	0	0
T16	0	32	0	0
T17	0	41	0	0
T18	0	10	0	0
T19	0	19	0	0
T20	0	23	0	0
T21	0	23	0	0
T22	0	16	0	0
T23	0	7	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1991	0	0
T14	253843	28	0	0
T15	0	5	0	0
T16	0	16	0	0
T17	0	18	0	0
T18	0	5	0	0
T19	0	21	0	0
T20	0	27	0	0
T21	0	16	0	0
T22	0	15	0	0
T23	0	18	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1699	0	0
T14	253843	22	0	0
T15	0	4	0	0
T16	0	21	0	0
T17	0	22	0	0
T18	0	22	0	0
T19	0	32	0	0
T20	0	21	0	0
T21	0	17	0	0
T22	0	22	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0
T33	0	21	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2325	0	0
T14	253843	14	0	0
T15	0	6	0	0
T16	0	38	0	0
T17	0	42	0	0
T18	0	12	0	0
T19	0	16	0	0
T20	0	29	0	0
T21	0	12	0	0
T22	0	26	0	0
T23	0	23	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1946	0	0
T14	253843	14	0	0
T15	0	17	0	0
T16	0	30	0	0
T17	0	38	0	0
T18	0	18	0	0
T19	0	12	0	0
T20	0	16	0	0
T21	0	30	0	0
T22	0	30	0	0
T23	0	3	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2214	0	0
T14	253843	4	0	0
T15	0	12	0	0
T16	0	20	0	0
T17	0	47	0	0
T18	0	17	0	0
T19	0	27	0	0
T20	0	21	0	0
T21	0	17	0	0
T22	0	27	0	0
T23	0	17	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1678	0	0
T14	253843	24	0	0
T15	0	9	0	0
T16	0	37	0	0
T17	0	42	0	0
T18	0	3	0	0
T19	0	14	0	0
T20	0	23	0	0
T21	0	15	0	0
T22	0	29	0	0
T23	0	21	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1813	0	0
T14	253843	26	0	0
T15	0	5	0	0
T16	0	24	0	0
T17	0	32	0	0
T18	0	14	0	0
T19	0	20	0	0
T20	0	30	0	0
T21	0	14	0	0
T22	0	25	0	0
T23	0	2	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2216	0	0
T14	253843	17	0	0
T15	0	15	0	0
T16	0	57	0	0
T17	0	47	0	0
T18	0	15	0	0
T19	0	16	0	0
T20	0	34	0	0
T21	0	26	0	0
T22	0	33	0	0
T24	117145	0	0	0
T25	737235	0	0	0
T26	595246	0	0	0
T27	156599	0	0	0
T28	125009	0	0	0
T29	711248	0	0	0
T30	786895	0	0	0
T31	119655	0	0	0
T32	811189	0	0	0
T34	0	27	0	0