Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1173524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1145872

1

T1

54

T2

6415

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2031357	1			T1	81		T2	12276		T4	8012
values[0x0]	143593	1			T1	34		T2	387		T3	21
values[0x1]	144446	1			T1	29		T2	399		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	940809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1378587

1

T1

71

T2

7705

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10654	1			T2	33		T4	47		T5	4
valid_sources[0x01]	7453	1			T2	34		T4	6		T5	11
valid_sources[0x02]	13504	1			T2	17		T4	65		T9	7
valid_sources[0x03]	7532	1			T2	5		T3	10		T4	38
valid_sources[0x04]	9374	1			T4	18		T5	6		T9	13
valid_sources[0x05]	15499	1			T2	119		T4	14		T5	3
valid_sources[0x06]	10577	1			T4	45		T6	2		T9	6
valid_sources[0x07]	9335	1			T2	45		T4	30		T9	9
valid_sources[0x08]	10789	1			T4	42		T5	7		T9	7
valid_sources[0x09]	11131	1			T2	4		T4	23		T5	5
valid_sources[0x0a]	6469	1			T2	125		T5	1		T9	11
valid_sources[0x0b]	15191	1			T4	42		T5	20		T6	3
valid_sources[0x0c]	6742	1			T2	6		T4	25		T5	3
valid_sources[0x0d]	10709	1			T2	59		T4	30		T5	2
valid_sources[0x0e]	7049	1			T4	32		T5	4		T9	12
valid_sources[0x0f]	6602	1			T2	15		T4	17		T5	5
valid_sources[0x10]	6412	1			T2	81		T4	47		T5	7
valid_sources[0x11]	7108	1			T2	24		T4	106		T5	4
valid_sources[0x12]	10849	1			T2	63		T4	69		T9	16
valid_sources[0x13]	7379	1			T2	30		T5	1		T9	60
valid_sources[0x14]	7498	1			T4	5		T5	7		T9	8
valid_sources[0x15]	6888	1			T2	137		T4	68		T5	3
valid_sources[0x16]	6430	1			T2	51		T4	14		T9	7
valid_sources[0x17]	10657	1			T2	79		T4	41		T5	4
valid_sources[0x18]	9588	1			T2	108		T4	61		T5	1
valid_sources[0x19]	7212	1			T2	43		T4	26		T5	1
valid_sources[0x1a]	13502	1			T2	47		T4	80		T9	15
valid_sources[0x1b]	6693	1			T2	37		T4	28		T5	3
valid_sources[0x1c]	9412	1			T2	34		T4	5		T5	7
valid_sources[0x1d]	6883	1			T2	119		T4	14		T9	13
valid_sources[0x1e]	14466	1			T4	26		T6	1		T9	23
valid_sources[0x1f]	6887	1			T4	137		T9	10		T13	8
valid_sources[0x20]	7293	1			T2	19		T4	22		T5	3
valid_sources[0x21]	13703	1			T2	59		T4	14		T5	23
valid_sources[0x22]	8760	1			T2	131		T4	14		T6	2
valid_sources[0x23]	7444	1			T2	32		T4	20		T5	11
valid_sources[0x24]	9220	1			T2	125		T4	32		T6	1
valid_sources[0x25]	7345	1			T2	140		T4	13		T6	1
valid_sources[0x26]	7538	1			T2	109		T4	46		T5	6
valid_sources[0x27]	9526	1			T4	30		T5	8		T9	8
valid_sources[0x28]	7646	1			T2	8		T4	13		T5	2
valid_sources[0x29]	13701	1			T2	106		T4	21		T5	7
valid_sources[0x2a]	19372	1			T2	27		T4	64		T9	13
valid_sources[0x2b]	6419	1			T2	69		T4	8		T5	5
valid_sources[0x2c]	6907	1			T2	280		T4	20		T9	5
valid_sources[0x2d]	10877	1			T2	36		T4	99		T6	1
valid_sources[0x2e]	15381	1			T2	6		T4	3		T6	1
valid_sources[0x2f]	6530	1			T2	10		T4	5		T9	2
valid_sources[0x30]	6414	1			T2	72		T5	12		T9	10
valid_sources[0x31]	7018	1			T2	262		T4	162		T5	17
valid_sources[0x32]	7413	1			T4	49		T6	2		T9	8
valid_sources[0x33]	11416	1			T2	23		T4	50		T9	3
valid_sources[0x34]	10638	1			T2	93		T5	1		T9	8
valid_sources[0x35]	7694	1			T2	6		T4	31		T5	5
valid_sources[0x36]	6882	1			T4	6		T5	2		T6	2
valid_sources[0x37]	6620	1			T2	24		T4	11		T5	3
valid_sources[0x38]	6487	1			T2	33		T4	43		T5	1
valid_sources[0x39]	11596	1			T2	65		T4	37		T5	7
valid_sources[0x3a]	6757	1			T2	131		T4	18		T5	6
valid_sources[0x3b]	9563	1			T4	74		T9	21		T13	17
valid_sources[0x3c]	7007	1			T2	220		T4	19		T5	3
valid_sources[0x3d]	6579	1			T5	1		T9	12		T12	7
valid_sources[0x3e]	6567	1			T2	27		T4	105		T5	6
valid_sources[0x3f]	6666	1			T2	66		T4	19		T5	1
valid_sources[0x40]	10871	1			T2	78		T4	98		T9	14
valid_sources[0x41]	10693	1			T2	20		T4	9		T5	2
valid_sources[0x42]	10514	1			T2	17		T4	25		T9	10
valid_sources[0x43]	6546	1			T2	130		T4	50		T5	3
valid_sources[0x44]	6378	1			T4	16		T5	2		T6	2
valid_sources[0x45]	6682	1			T4	18		T10	1		T13	9
valid_sources[0x46]	11475	1			T4	21		T9	5		T12	31
valid_sources[0x47]	15337	1			T4	33		T5	2		T6	2
valid_sources[0x48]	6511	1			T2	96		T4	23		T5	13
valid_sources[0x49]	11285	1			T2	22		T4	2		T5	8
valid_sources[0x4a]	8824	1			T2	94		T4	14		T5	5
valid_sources[0x4b]	6999	1			T2	38		T4	91		T5	3
valid_sources[0x4c]	9429	1			T2	44		T4	1		T6	1
valid_sources[0x4d]	15490	1			T2	32		T4	6		T5	6
valid_sources[0x4e]	8333	1			T2	30		T4	10		T9	18
valid_sources[0x4f]	9369	1			T2	163		T4	28		T6	3
valid_sources[0x50]	7081	1			T2	23		T4	5		T5	1
valid_sources[0x51]	11783	1			T2	18		T4	22		T6	1
valid_sources[0x52]	7665	1			T2	26		T4	19		T9	21
valid_sources[0x53]	6953	1			T2	173		T4	94		T5	1
valid_sources[0x54]	6582	1			T2	78		T4	25		T5	5
valid_sources[0x55]	11588	1			T2	14		T4	7		T5	17
valid_sources[0x56]	6747	1			T2	72		T4	51		T6	1
valid_sources[0x57]	7647	1			T2	159		T4	98		T5	2
valid_sources[0x58]	6775	1			T2	44		T4	33		T9	11
valid_sources[0x59]	7455	1			T2	87		T4	8		T9	14
valid_sources[0x5a]	6544	1			T2	223		T4	34		T5	4
valid_sources[0x5b]	18076	1			T2	126		T4	10		T5	14
valid_sources[0x5c]	6682	1			T5	5		T9	7		T13	19
valid_sources[0x5d]	6755	1			T2	27		T5	1		T6	2
valid_sources[0x5e]	11693	1			T2	67		T4	9		T5	3
valid_sources[0x5f]	6811	1			T2	118		T4	44		T5	1
valid_sources[0x60]	11788	1			T2	2		T4	14		T9	13
valid_sources[0x61]	11077	1			T2	37		T4	15		T5	2
valid_sources[0x62]	6549	1			T2	51		T4	55		T9	16
valid_sources[0x63]	7089	1			T2	4		T4	18		T5	2
valid_sources[0x64]	6820	1			T2	2		T4	13		T5	4
valid_sources[0x65]	7389	1			T4	37		T9	9		T13	26
valid_sources[0x66]	6622	1			T2	13		T4	15		T9	6
valid_sources[0x67]	6466	1			T2	161		T4	40		T5	4
valid_sources[0x68]	8366	1			T4	6		T5	1		T9	10
valid_sources[0x69]	24262	1			T2	48		T4	30		T5	22
valid_sources[0x6a]	10900	1			T2	4		T4	26		T5	4
valid_sources[0x6b]	6627	1			T2	56		T4	67		T5	2
valid_sources[0x6c]	7765	1			T4	101		T6	1		T9	4
valid_sources[0x6d]	14774	1			T9	8		T13	36		T14	2
valid_sources[0x6e]	7125	1			T2	352		T4	39		T6	1
valid_sources[0x6f]	7942	1			T2	25		T4	61		T6	2
valid_sources[0x70]	6385	1			T5	1		T6	1		T9	7
valid_sources[0x71]	6399	1			T2	27		T4	8		T5	2
valid_sources[0x72]	15956	1			T4	59		T5	3		T6	3
valid_sources[0x73]	12308	1			T2	17		T9	10		T15	2
valid_sources[0x74]	7157	1			T2	116		T4	32		T6	3
valid_sources[0x75]	6516	1			T2	28		T4	2		T5	1
valid_sources[0x76]	7719	1			T2	97		T4	12		T5	6
valid_sources[0x77]	6968	1			T2	48		T3	4		T4	17
valid_sources[0x78]	7525	1			T4	79		T5	15		T9	18
valid_sources[0x79]	8875	1			T2	232		T4	15		T5	5
valid_sources[0x7a]	6643	1			T2	28		T4	58		T5	5
valid_sources[0x7b]	6757	1			T2	48		T4	28		T9	4
valid_sources[0x7c]	10626	1			T2	10		T4	43		T9	8
valid_sources[0x7d]	6754	1			T2	41		T4	34		T6	2
valid_sources[0x7e]	7439	1			T2	16		T4	39		T6	1
valid_sources[0x7f]	10894	1			T2	27		T4	29		T9	31
valid_sources[0x80]	8289	1			T2	17		T4	6		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1011907

1

T1

33

T2

6099

T4

4039

values[0x0]

all_enables

biggest_size

77801

1

T1

15

T2

198

T3

10

values[0x1]

all_enables

biggest_size

56164

1

T1

6

T2

118

T3

13