Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28068	1			T2	24		T4	17		T5	17
auto[PWRUP]	97	1			T29	1		T46	2		T47	1
auto[ONEST_0]	68	1			T29	1		T49	1		T48	1
auto[ONEST_021]	13	1			T49	1		T187	2		T216	1
auto[ONEST_1]	71	1			T29	1		T46	1		T49	1
auto[ONEST_DONE]	6	1			T47	1		T217	1		T218	2
auto[LP_0]	127	1			T29	1		T46	2		T47	3
auto[LP_021]	33	1			T48	2		T50	1		T187	2
auto[LP_1]	122	1			T46	1		T47	1		T49	3
auto[LP_EVAL]	59	1			T29	1		T47	2		T34	1
auto[LP_SLP]	473	1			T29	2		T46	6		T47	9
auto[LP_PWRUP]	20	1			T29	1		T48	1		T187	2
auto[NP_0]	147	1			T29	1		T46	4		T47	5
auto[NP_021]	45	1			T49	1		T37	1		T187	3
auto[NP_1]	170	1			T46	2		T49	5		T48	3
auto[NP_EVAL]	30	1			T29	2		T37	1		T187	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T219

1

T220

1

T217

1

min

27562

1

T2

24

T4

17

T5

17

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27570	1			T2	24		T4	17		T5	17
pow[0x1]	5	1			T50	1		T219	1		T221	1
pow[0x2]	19	1			T47	1		T48	1		T187	1
pow[0x3]	29	1			T48	2		T50	1		T187	1
pow[0x4]	62	1			T29	2		T46	3		T47	2
pow[0x5]	110	1			T46	3		T47	2		T49	1
pow[0x6]	246	1			T29	2		T46	4		T47	5
pow[0x7]	479	1			T29	4		T46	12		T47	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

174

1

T29

2

T46

2

T47

3

min

27143

1

T2

24

T4

17

T5

17

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27143	1			T2	24		T4	17		T5	17
pow[0x5]	1	1			T220	1		-	-		-	-
pow[0x6]	2	1			T222	1		T223	1		-	-
pow[0x7]	2	1			T187	1		T224	1		-	-
pow[0x8]	4	1			T48	1		T225	1		T226	1
pow[0x9]	9	1			T29	1		T50	1		T222	1
pow[0xa]	15	1			T46	1		T187	1		T227	1
pow[0xb]	35	1			T47	1		T49	1		T187	1
pow[0xc]	73	1			T29	1		T46	1		T47	1
pow[0xd]	161	1			T29	2		T46	4		T47	4
pow[0xe]	298	1			T29	3		T46	5		T47	8
pow[0xf]	544	1			T29	1		T46	11		T47	8