Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	2	15	88.24	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	2	15	88.24

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ONEST_DONE]	0	1	1
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2235	1			T13	12		T14	8		T29	14
auto[PWRUP]	148	1			T29	3		T47	1		T35	1
auto[ONEST_0]	65	1			T14	1		T46	1		T49	1
auto[ONEST_021]	23	1			T46	1		T48	1		T50	1
auto[ONEST_1]	99	1			T14	1		T29	1		T46	2
auto[LP_0]	117	1			T29	1		T47	3		T35	1
auto[LP_021]	29	1			T29	2		T46	1		T47	1
auto[LP_1]	110	1			T29	1		T47	1		T35	2
auto[LP_EVAL]	52	1			T29	1		T47	1		T49	1
auto[LP_SLP]	564	1			T13	2		T29	4		T46	7
auto[LP_PWRUP]	25	1			T17	1		T50	1		T219	1
auto[NP_0]	213	1			T14	2		T29	1		T46	3
auto[NP_021]	51	1			T47	3		T49	2		T50	3
auto[NP_1]	219	1			T13	7		T14	1		T46	2
auto[NP_EVAL]	31	1			T33	1		T48	2		T36	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T49

1

T187

1

T216

1

min

1931

1

T13

20

T14

13

T29

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1940	1			T13	21		T14	13		T29	8
pow[0x1]	13	1			T29	1		T225	1		T356	1
pow[0x2]	15	1			T46	1		T47	1		T187	1
pow[0x3]	32	1			T46	1		T48	2		T37	1
pow[0x4]	80	1			T29	2		T46	1		T47	2
pow[0x5]	133	1			T46	1		T47	7		T35	1
pow[0x6]	256	1			T29	1		T46	6		T47	4
pow[0x7]	516	1			T29	4		T46	8		T47	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

162

1

T46

3

T47

3

T48

6

min

1333

1

T13

15

T14

11

T40

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1341	1			T13	16		T14	11		T40	5
pow[0x1]	12	1			T13	1		T23	3		T338	2
pow[0x2]	21	1			T33	1		T35	1		T37	1
pow[0x3]	49	1			T16	1		T35	1		T37	5
pow[0x4]	49	1			T13	4		T14	2		T33	2
pow[0x5]	1	1			T357	1		-	-		-	-
pow[0x6]	2	1			T256	1		T358	1		-	-
pow[0x7]	3	1			T359	1		T360	1		T361	1
pow[0x8]	3	1			T106	1		T361	1		T292	1
pow[0x9]	7	1			T48	1		T362	1		T256	1
pow[0xa]	21	1			T47	1		T16	1		T50	1
pow[0xb]	45	1			T35	1		T49	1		T48	1
pow[0xc]	74	1			T29	1		T46	1		T48	1
pow[0xd]	151	1			T29	3		T46	4		T47	1
pow[0xe]	300	1			T29	2		T46	3		T47	4
pow[0xf]	592	1			T29	3		T46	11		T47	6