Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2222	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2054	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2350	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2321	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2212	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2216	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2118	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2136	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2179	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2084	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2222	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2360	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2234	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2074	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2063	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2154	0	0
adc_en_ctl_rd_A	2147483647	1735	0	0
adc_fsm_rst_rd_A	2147483647	1367	0	0
adc_intr_ctl_rd_A	2147483647	2368	0	0
adc_lp_sample_ctl_rd_A	2147483647	1377	0	0
adc_pd_ctl_rd_A	2147483647	1861	0	0
adc_sample_ctl_rd_A	2147483647	1345	0	0
adc_wakeup_ctl_rd_A	2147483647	1763	0	0
intr_enable_rd_A	2147483647	2331	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2222	0	0
T13	789269	40	0	0
T14	232404	22	0	0
T16	0	18	0	0
T17	0	16	0	0
T18	0	14	0	0
T19	0	26	0	0
T20	0	1	0	0
T21	0	18	0	0
T22	0	22	0	0
T23	0	27	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2054	0	0
T13	789269	51	0	0
T14	232404	8	0	0
T16	0	21	0	0
T17	0	12	0	0
T18	0	4	0	0
T19	0	42	0	0
T20	0	10	0	0
T21	0	25	0	0
T22	0	8	0	0
T23	0	26	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2350	0	0
T13	789269	46	0	0
T14	232404	11	0	0
T16	0	25	0	0
T17	0	12	0	0
T18	0	18	0	0
T19	0	37	0	0
T20	0	25	0	0
T21	0	12	0	0
T22	0	7	0	0
T23	0	27	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2321	0	0
T13	789269	28	0	0
T14	232404	6	0	0
T16	0	23	0	0
T17	0	6	0	0
T18	0	25	0	0
T19	0	33	0	0
T20	0	6	0	0
T21	0	35	0	0
T22	0	22	0	0
T23	0	41	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2212	0	0
T13	789269	51	0	0
T14	232404	7	0	0
T16	0	28	0	0
T17	0	5	0	0
T18	0	14	0	0
T19	0	45	0	0
T20	0	8	0	0
T21	0	13	0	0
T22	0	12	0	0
T23	0	22	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2216	0	0
T13	789269	41	0	0
T14	232404	6	0	0
T16	0	26	0	0
T17	0	18	0	0
T18	0	16	0	0
T19	0	45	0	0
T20	0	11	0	0
T21	0	25	0	0
T22	0	20	0	0
T23	0	16	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2118	0	0
T13	789269	26	0	0
T14	232404	17	0	0
T16	0	26	0	0
T17	0	5	0	0
T18	0	12	0	0
T19	0	50	0	0
T20	0	22	0	0
T21	0	19	0	0
T22	0	23	0	0
T23	0	21	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2136	0	0
T13	789269	39	0	0
T14	232404	7	0	0
T16	0	12	0	0
T17	0	10	0	0
T18	0	16	0	0
T19	0	36	0	0
T20	0	3	0	0
T21	0	7	0	0
T22	0	19	0	0
T23	0	20	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2179	0	0
T13	789269	42	0	0
T14	232404	17	0	0
T16	0	12	0	0
T17	0	11	0	0
T18	0	23	0	0
T19	0	36	0	0
T20	0	12	0	0
T21	0	19	0	0
T22	0	9	0	0
T23	0	20	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2084	0	0
T13	789269	25	0	0
T14	232404	13	0	0
T16	0	24	0	0
T17	0	10	0	0
T18	0	18	0	0
T19	0	29	0	0
T20	0	7	0	0
T21	0	19	0	0
T22	0	27	0	0
T23	0	7	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2222	0	0
T13	789269	35	0	0
T14	232404	14	0	0
T16	0	22	0	0
T17	0	13	0	0
T18	0	17	0	0
T19	0	40	0	0
T20	0	15	0	0
T21	0	23	0	0
T22	0	21	0	0
T23	0	7	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2360	0	0
T13	789269	56	0	0
T14	232404	21	0	0
T16	0	9	0	0
T17	0	9	0	0
T18	0	21	0	0
T19	0	24	0	0
T20	0	1	0	0
T21	0	33	0	0
T22	0	10	0	0
T23	0	22	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2234	0	0
T13	789269	37	0	0
T14	232404	8	0	0
T16	0	29	0	0
T17	0	6	0	0
T18	0	14	0	0
T19	0	20	0	0
T20	0	5	0	0
T21	0	18	0	0
T22	0	15	0	0
T23	0	14	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2074	0	0
T13	789269	44	0	0
T14	232404	11	0	0
T16	0	17	0	0
T17	0	13	0	0
T18	0	26	0	0
T19	0	36	0	0
T20	0	8	0	0
T21	0	26	0	0
T22	0	16	0	0
T23	0	12	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2063	0	0
T13	789269	50	0	0
T14	232404	7	0	0
T16	0	13	0	0
T17	0	18	0	0
T18	0	14	0	0
T19	0	30	0	0
T20	0	11	0	0
T21	0	25	0	0
T22	0	2	0	0
T23	0	16	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2154	0	0
T13	789269	41	0	0
T14	232404	11	0	0
T16	0	22	0	0
T17	0	13	0	0
T18	0	17	0	0
T19	0	32	0	0
T20	0	17	0	0
T21	0	9	0	0
T22	0	7	0	0
T23	0	31	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1735	0	0
T13	789269	54	0	0
T14	232404	17	0	0
T16	0	13	0	0
T17	0	14	0	0
T18	0	17	0	0
T19	0	33	0	0
T20	0	10	0	0
T21	0	23	0	0
T22	0	12	0	0
T23	0	26	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1367	0	0
T13	789269	34	0	0
T14	232404	14	0	0
T16	0	18	0	0
T17	0	2	0	0
T18	0	26	0	0
T19	0	36	0	0
T20	0	15	0	0
T21	0	25	0	0
T22	0	6	0	0
T23	0	17	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2368	0	0
T13	789269	42	0	0
T14	232404	10	0	0
T16	0	27	0	0
T17	0	10	0	0
T18	0	28	0	0
T19	0	42	0	0
T21	0	23	0	0
T22	0	16	0	0
T23	0	19	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0
T32	0	26	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1377	0	0
T13	789269	46	0	0
T14	232404	10	0	0
T16	0	22	0	0
T17	0	14	0	0
T18	0	17	0	0
T19	0	33	0	0
T20	0	4	0	0
T21	0	31	0	0
T22	0	13	0	0
T23	0	3	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1861	0	0
T13	789269	51	0	0
T14	232404	15	0	0
T16	0	21	0	0
T17	0	12	0	0
T18	0	10	0	0
T19	0	37	0	0
T20	0	16	0	0
T21	0	14	0	0
T22	0	5	0	0
T23	0	10	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1345	0	0
T13	789269	38	0	0
T14	232404	6	0	0
T16	0	19	0	0
T17	0	12	0	0
T18	0	18	0	0
T19	0	35	0	0
T20	0	3	0	0
T21	0	21	0	0
T22	0	19	0	0
T23	0	12	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1763	0	0
T13	789269	32	0	0
T14	232404	11	0	0
T16	0	11	0	0
T17	0	16	0	0
T18	0	16	0	0
T19	0	51	0	0
T20	0	21	0	0
T21	0	21	0	0
T22	0	11	0	0
T23	0	16	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2331	0	0
T13	789269	54	0	0
T14	232404	25	0	0
T16	0	33	0	0
T17	0	14	0	0
T18	0	39	0	0
T19	0	37	0	0
T20	0	18	0	0
T21	0	21	0	0
T22	0	42	0	0
T23	0	26	0	0
T24	592585	0	0	0
T25	136090	0	0	0
T26	779647	0	0	0
T27	301798	0	0	0
T28	50970	0	0	0
T29	191823	0	0	0
T30	451765	0	0	0
T31	177498	0	0	0