Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1174228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1149712

1

T1

2066

T2

6315

T3

6742

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2029209	1			T1	3875		T2	12103		T3	12182
values[0x0]	146696	1			T1	129		T2	390		T3	823
values[0x1]	148035	1			T1	128		T2	378		T3	824

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	941042	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1382898

1

T1

2486

T2

7644

T3

8097

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9418	1			T1	14		T2	51		T3	79
valid_sources[0x01]	7822	1			T1	13		T2	46		T3	54
valid_sources[0x02]	12467	1			T1	11		T2	41		T3	49
valid_sources[0x03]	9864	1			T1	15		T2	50		T3	45
valid_sources[0x04]	6828	1			T1	14		T2	41		T3	49
valid_sources[0x05]	6627	1			T1	11		T2	54		T3	41
valid_sources[0x06]	6713	1			T1	20		T2	62		T3	36
valid_sources[0x07]	6845	1			T1	15		T2	52		T3	28
valid_sources[0x08]	10881	1			T1	18		T2	40		T3	74
valid_sources[0x09]	11377	1			T1	12		T2	47		T3	69
valid_sources[0x0a]	6961	1			T1	18		T2	44		T3	43
valid_sources[0x0b]	7364	1			T1	18		T2	39		T3	43
valid_sources[0x0c]	7000	1			T1	22		T2	68		T3	38
valid_sources[0x0d]	7018	1			T1	18		T2	44		T3	57
valid_sources[0x0e]	7474	1			T1	13		T2	57		T3	71
valid_sources[0x0f]	7003	1			T1	11		T2	53		T3	49
valid_sources[0x10]	7971	1			T1	8		T2	46		T3	54
valid_sources[0x11]	6883	1			T1	16		T2	80		T3	55
valid_sources[0x12]	6771	1			T1	12		T2	50		T3	61
valid_sources[0x13]	7718	1			T1	20		T2	59		T3	51
valid_sources[0x14]	7249	1			T1	24		T2	57		T3	50
valid_sources[0x15]	12417	1			T1	23		T2	67		T3	49
valid_sources[0x16]	7022	1			T1	23		T2	47		T3	54
valid_sources[0x17]	8929	1			T1	13		T2	38		T3	64
valid_sources[0x18]	8640	1			T1	13		T2	51		T3	34
valid_sources[0x19]	6658	1			T1	17		T2	41		T3	67
valid_sources[0x1a]	6780	1			T1	14		T2	50		T3	45
valid_sources[0x1b]	6857	1			T1	20		T2	61		T3	58
valid_sources[0x1c]	7013	1			T1	26		T2	73		T3	42
valid_sources[0x1d]	9557	1			T1	11		T2	37		T3	41
valid_sources[0x1e]	7569	1			T1	19		T2	28		T3	54
valid_sources[0x1f]	9710	1			T1	12		T2	51		T3	60
valid_sources[0x20]	6813	1			T1	18		T2	45		T3	55
valid_sources[0x21]	6966	1			T1	15		T2	46		T3	42
valid_sources[0x22]	7106	1			T1	18		T2	58		T3	52
valid_sources[0x23]	19336	1			T1	19		T2	52		T3	48
valid_sources[0x24]	6805	1			T1	21		T2	44		T3	94
valid_sources[0x25]	6987	1			T1	12		T2	71		T3	77
valid_sources[0x26]	6500	1			T1	17		T2	49		T3	47
valid_sources[0x27]	6882	1			T1	13		T2	64		T3	48
valid_sources[0x28]	6580	1			T1	16		T2	84		T3	46
valid_sources[0x29]	11226	1			T1	20		T2	34		T3	29
valid_sources[0x2a]	15152	1			T1	15		T2	79		T3	62
valid_sources[0x2b]	15564	1			T1	15		T2	73		T3	62
valid_sources[0x2c]	7999	1			T1	17		T2	42		T3	68
valid_sources[0x2d]	9242	1			T1	18		T2	56		T3	93
valid_sources[0x2e]	11329	1			T1	14		T2	55		T3	47
valid_sources[0x2f]	7478	1			T1	17		T2	69		T3	46
valid_sources[0x30]	15805	1			T1	19		T2	40		T3	33
valid_sources[0x31]	7135	1			T1	20		T2	70		T3	35
valid_sources[0x32]	7071	1			T1	18		T2	43		T3	27
valid_sources[0x33]	7738	1			T1	17		T2	38		T3	59
valid_sources[0x34]	11252	1			T1	18		T2	43		T3	41
valid_sources[0x35]	12360	1			T1	16		T2	64		T3	56
valid_sources[0x36]	6844	1			T1	25		T2	33		T3	62
valid_sources[0x37]	7605	1			T1	13		T2	49		T3	56
valid_sources[0x38]	7941	1			T1	17		T2	49		T3	56
valid_sources[0x39]	6582	1			T1	19		T2	78		T3	64
valid_sources[0x3a]	8681	1			T1	15		T2	48		T3	27
valid_sources[0x3b]	6690	1			T1	19		T2	39		T3	74
valid_sources[0x3c]	8441	1			T1	19		T2	55		T3	56
valid_sources[0x3d]	7824	1			T1	11		T2	46		T3	59
valid_sources[0x3e]	11033	1			T1	23		T2	58		T3	54
valid_sources[0x3f]	12358	1			T1	16		T2	44		T3	44
valid_sources[0x40]	6461	1			T1	15		T2	38		T3	72
valid_sources[0x41]	7015	1			T1	17		T2	51		T3	69
valid_sources[0x42]	7078	1			T1	21		T2	27		T3	62
valid_sources[0x43]	6759	1			T1	26		T2	41		T3	65
valid_sources[0x44]	11409	1			T1	19		T2	44		T3	42
valid_sources[0x45]	11554	1			T1	15		T2	64		T3	55
valid_sources[0x46]	10522	1			T1	20		T2	88		T3	50
valid_sources[0x47]	11308	1			T1	12		T2	42		T3	66
valid_sources[0x48]	11386	1			T1	16		T2	27		T3	46
valid_sources[0x49]	7730	1			T1	10		T2	42		T3	32
valid_sources[0x4a]	6938	1			T1	14		T2	34		T3	32
valid_sources[0x4b]	6746	1			T1	20		T2	55		T3	57
valid_sources[0x4c]	8026	1			T1	17		T2	42		T3	63
valid_sources[0x4d]	7238	1			T1	13		T2	49		T3	40
valid_sources[0x4e]	7555	1			T1	22		T2	54		T3	42
valid_sources[0x4f]	15339	1			T1	15		T2	46		T3	58
valid_sources[0x50]	7212	1			T1	14		T2	48		T3	84
valid_sources[0x51]	7809	1			T1	10		T2	69		T3	25
valid_sources[0x52]	6740	1			T1	15		T2	43		T3	52
valid_sources[0x53]	13960	1			T1	10		T2	42		T3	43
valid_sources[0x54]	8189	1			T1	14		T2	74		T3	67
valid_sources[0x55]	6706	1			T1	17		T2	73		T3	49
valid_sources[0x56]	11916	1			T1	24		T2	40		T3	65
valid_sources[0x57]	12123	1			T1	23		T2	39		T3	54
valid_sources[0x58]	11070	1			T1	18		T2	42		T3	73
valid_sources[0x59]	7189	1			T1	14		T2	41		T3	51
valid_sources[0x5a]	7812	1			T1	17		T2	40		T3	43
valid_sources[0x5b]	9394	1			T1	14		T2	35		T3	62
valid_sources[0x5c]	6533	1			T1	21		T2	65		T3	36
valid_sources[0x5d]	6936	1			T1	11		T2	52		T3	60
valid_sources[0x5e]	6988	1			T1	17		T2	51		T3	56
valid_sources[0x5f]	6849	1			T1	15		T2	54		T3	68
valid_sources[0x60]	8500	1			T1	24		T2	27		T3	71
valid_sources[0x61]	10841	1			T1	17		T2	53		T3	82
valid_sources[0x62]	6722	1			T1	17		T2	59		T3	67
valid_sources[0x63]	7158	1			T1	13		T2	54		T3	43
valid_sources[0x64]	6805	1			T1	15		T2	43		T3	68
valid_sources[0x65]	10408	1			T1	21		T2	41		T3	76
valid_sources[0x66]	12376	1			T1	18		T2	59		T3	65
valid_sources[0x67]	7077	1			T1	10		T2	48		T3	53
valid_sources[0x68]	6910	1			T1	13		T2	35		T3	54
valid_sources[0x69]	11067	1			T1	19		T2	40		T3	67
valid_sources[0x6a]	8737	1			T1	9		T2	49		T3	48
valid_sources[0x6b]	6941	1			T1	15		T2	38		T3	39
valid_sources[0x6c]	10753	1			T1	22		T2	41		T3	47
valid_sources[0x6d]	19910	1			T1	18		T2	59		T3	72
valid_sources[0x6e]	6903	1			T1	11		T2	53		T3	79
valid_sources[0x6f]	6820	1			T1	26		T2	52		T3	52
valid_sources[0x70]	10022	1			T1	14		T2	49		T3	41
valid_sources[0x71]	8472	1			T1	11		T2	60		T3	53
valid_sources[0x72]	6846	1			T1	16		T2	53		T3	48
valid_sources[0x73]	9164	1			T1	18		T2	56		T3	39
valid_sources[0x74]	6779	1			T1	10		T2	77		T3	30
valid_sources[0x75]	6973	1			T1	15		T2	51		T3	59
valid_sources[0x76]	7016	1			T1	10		T2	59		T3	29
valid_sources[0x77]	6826	1			T1	16		T2	41		T3	36
valid_sources[0x78]	6804	1			T1	21		T2	53		T3	55
valid_sources[0x79]	6885	1			T1	13		T2	61		T3	48
valid_sources[0x7a]	10578	1			T1	16		T2	39		T3	75
valid_sources[0x7b]	6408	1			T1	21		T2	45		T3	30
valid_sources[0x7c]	6789	1			T1	19		T2	42		T3	68
valid_sources[0x7d]	6492	1			T1	23		T2	43		T3	78
valid_sources[0x7e]	23941	1			T1	14		T2	50		T3	50
valid_sources[0x7f]	6777	1			T1	16		T2	42		T3	31
valid_sources[0x80]	7529	1			T1	27		T2	59		T3	65

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1011922

1

T1

1969

T2

6008

T3

6125

values[0x0]

all_enables

biggest_size

80096

1

T1

58

T2

200

T3

378

values[0x1]

all_enables

biggest_size

57694

1

T1

39

T2

107

T3

239