Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	32206	1			T1	9		T2	19		T3	183
auto[PWRUP]	131	1			T9	2		T218	2		T49	3
auto[ONEST_0]	76	1			T9	1		T11	1		T23	1
auto[ONEST_021]	18	1			T46	1		T219	1		T220	1
auto[ONEST_1]	79	1			T9	1		T11	1		T23	2
auto[ONEST_DONE]	5	1			T35	1		T221	1		T222	1
auto[LP_0]	139	1			T3	1		T9	3		T23	2
auto[LP_021]	31	1			T23	1		T46	1		T223	3
auto[LP_1]	122	1			T3	2		T9	1		T23	3
auto[LP_EVAL]	71	1			T3	1		T11	1		T23	1
auto[LP_SLP]	486	1			T3	1		T9	6		T11	1
auto[LP_PWRUP]	26	1			T9	1		T13	1		T218	1
auto[NP_0]	170	1			T3	1		T9	5		T11	1
auto[NP_021]	28	1			T23	1		T224	2		T82	1
auto[NP_1]	167	1			T3	1		T9	2		T11	1
auto[NP_EVAL]	26	1			T9	1		T49	1		T224	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T23

1

T46

1

T225

1

min

31609

1

T1

9

T2

19

T3

170

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31622	1			T1	9		T2	19		T3	170
pow[0x1]	12	1			T81	1		T220	1		T226	1
pow[0x2]	20	1			T9	2		T49	1		T225	1
pow[0x3]	34	1			T11	1		T46	1		T218	1
pow[0x4]	56	1			T3	1		T9	1		T11	1
pow[0x5]	141	1			T3	2		T9	1		T23	1
pow[0x6]	278	1			T3	2		T9	6		T23	6
pow[0x7]	543	1			T3	3		T9	8		T23	11

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

209

1

T9

4

T11

1

T23

6

min

31170

1

T1

9

T2

19

T3

168

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31171	1			T1	9		T2	19		T3	168
pow[0x4]	1	1			T227	1		-	-		-	-
pow[0x6]	3	1			T228	1		T185	1		T229	1
pow[0x7]	1	1			T225	1		-	-		-	-
pow[0x8]	5	1			T23	1		T218	1		T48	1
pow[0x9]	6	1			T218	1		T81	1		T230	1
pow[0xa]	22	1			T225	1		T220	1		T37	1
pow[0xb]	40	1			T23	2		T47	1		T223	1
pow[0xc]	92	1			T23	2		T47	1		T46	1
pow[0xd]	143	1			T3	1		T9	2		T11	2
pow[0xe]	296	1			T3	4		T9	3		T23	6
pow[0xf]	576	1			T3	3		T9	7		T11	1