Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2396	1			T3	21		T9	22		T11	14
auto[PWRUP]	116	1			T9	1		T11	1		T23	2
auto[ONEST_0]	79	1			T9	1		T224	2		T223	1
auto[ONEST_021]	28	1			T23	1		T46	1		T49	1
auto[ONEST_1]	102	1			T9	1		T23	2		T34	1
auto[ONEST_DONE]	4	1			T37	1		T228	1		T190	1
auto[LP_0]	143	1			T3	1		T9	2		T34	1
auto[LP_021]	33	1			T9	4		T11	1		T34	1
auto[LP_1]	134	1			T3	2		T9	1		T11	2
auto[LP_EVAL]	53	1			T3	1		T11	1		T47	1
auto[LP_SLP]	543	1			T3	9		T9	5		T23	8
auto[LP_PWRUP]	30	1			T46	1		T49	1		T225	1
auto[NP_0]	245	1			T3	1		T9	6		T11	2
auto[NP_021]	44	1			T3	1		T23	1		T47	1
auto[NP_1]	260	1			T3	3		T9	2		T23	7
auto[NP_EVAL]	22	1			T81	1		T365	1		T226	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T23

1

T366

1

T367

1

min

2044

1

T3

16

T9

13

T11

15

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2059	1			T3	16		T9	13		T11	15
pow[0x1]	12	1			T224	1		T48	1		T368	1
pow[0x2]	18	1			T49	1		T224	1		T35	2
pow[0x3]	31	1			T9	2		T13	1		T47	1
pow[0x4]	80	1			T3	3		T11	1		T23	3
pow[0x5]	143	1			T3	2		T9	1		T23	2
pow[0x6]	294	1			T3	5		T9	4		T11	1
pow[0x7]	537	1			T3	5		T9	10		T11	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

201

1

T3

3

T9

4

T23

3

min

1430

1

T3

5

T9

7

T11

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1440	1			T3	5		T9	7		T11	10
pow[0x1]	22	1			T13	1		T35	3		T36	1
pow[0x2]	26	1			T11	1		T25	1		T37	1
pow[0x3]	42	1			T34	1		T37	2		T38	1
pow[0x4]	52	1			T11	1		T34	1		T36	2
pow[0x6]	3	1			T331	1		T369	1		T370	1
pow[0x7]	5	1			T368	1		T45	1		T221	1
pow[0x8]	3	1			T339	1		T331	1		T371	1
pow[0x9]	9	1			T13	1		T46	1		T218	1
pow[0xa]	19	1			T47	1		T46	1		T224	2
pow[0xb]	39	1			T9	2		T46	1		T218	1
pow[0xc]	68	1			T23	4		T46	2		T218	2
pow[0xd]	140	1			T3	4		T9	1		T23	2
pow[0xe]	301	1			T3	3		T9	4		T11	2
pow[0xf]	580	1			T3	6		T9	8		T11	4