Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1496	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1467	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1538	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1463	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1519	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1495	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1565	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1564	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1363	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1442	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1513	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1558	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1621	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1541	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1424	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1491	0	0
adc_en_ctl_rd_A	2147483647	1279	0	0
adc_fsm_rst_rd_A	2147483647	1353	0	0
adc_intr_ctl_rd_A	2147483647	1342	0	0
adc_lp_sample_ctl_rd_A	2147483647	1406	0	0
adc_pd_ctl_rd_A	2147483647	1347	0	0
adc_sample_ctl_rd_A	2147483647	1335	0	0
adc_wakeup_ctl_rd_A	2147483647	1372	0	0
intr_enable_rd_A	2147483647	1625	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1496	0	0
T11	146984	20	0	0
T12	195963	0	0	0
T13	0	25	0	0
T14	0	25	0	0
T15	0	23	0	0
T16	0	39	0	0
T17	0	28	0	0
T18	0	50	0	0
T19	0	19	0	0
T20	0	22	0	0
T21	0	26	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1467	0	0
T11	146984	11	0	0
T12	195963	0	0	0
T13	0	23	0	0
T14	0	31	0	0
T15	0	6	0	0
T16	0	45	0	0
T17	0	14	0	0
T18	0	52	0	0
T19	0	12	0	0
T20	0	13	0	0
T21	0	13	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T11	146984	23	0	0
T12	195963	0	0	0
T13	0	25	0	0
T14	0	28	0	0
T15	0	20	0	0
T16	0	32	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	0	1	0	0
T20	0	7	0	0
T21	0	35	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1463	0	0
T11	146984	21	0	0
T12	195963	0	0	0
T13	0	12	0	0
T14	0	15	0	0
T15	0	18	0	0
T16	0	50	0	0
T17	0	17	0	0
T18	0	39	0	0
T19	0	11	0	0
T20	0	15	0	0
T21	0	18	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1519	0	0
T11	146984	17	0	0
T12	195963	0	0	0
T13	0	17	0	0
T14	0	33	0	0
T15	0	19	0	0
T16	0	32	0	0
T17	0	23	0	0
T18	0	28	0	0
T19	0	2	0	0
T20	0	20	0	0
T21	0	40	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1495	0	0
T11	146984	23	0	0
T12	195963	0	0	0
T13	0	18	0	0
T14	0	29	0	0
T15	0	20	0	0
T16	0	24	0	0
T17	0	19	0	0
T18	0	36	0	0
T19	0	2	0	0
T20	0	15	0	0
T21	0	35	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T11	146984	12	0	0
T12	195963	0	0	0
T13	0	19	0	0
T14	0	23	0	0
T15	0	21	0	0
T16	0	36	0	0
T17	0	18	0	0
T18	0	40	0	0
T19	0	16	0	0
T20	0	25	0	0
T21	0	13	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1564	0	0
T11	146984	9	0	0
T12	195963	0	0	0
T13	0	17	0	0
T14	0	29	0	0
T15	0	20	0	0
T16	0	25	0	0
T17	0	33	0	0
T18	0	24	0	0
T19	0	9	0	0
T20	0	27	0	0
T21	0	28	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1363	0	0
T11	146984	5	0	0
T12	195963	0	0	0
T13	0	19	0	0
T14	0	28	0	0
T15	0	27	0	0
T16	0	41	0	0
T17	0	18	0	0
T18	0	49	0	0
T19	0	6	0	0
T20	0	27	0	0
T21	0	38	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1442	0	0
T11	146984	12	0	0
T12	195963	0	0	0
T13	0	16	0	0
T14	0	13	0	0
T15	0	10	0	0
T16	0	19	0	0
T17	0	34	0	0
T18	0	33	0	0
T19	0	3	0	0
T20	0	17	0	0
T21	0	19	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T11	146984	18	0	0
T12	195963	0	0	0
T13	0	26	0	0
T14	0	22	0	0
T15	0	13	0	0
T16	0	24	0	0
T17	0	14	0	0
T18	0	45	0	0
T19	0	9	0	0
T20	0	22	0	0
T21	0	20	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1558	0	0
T11	146984	21	0	0
T12	195963	0	0	0
T13	0	24	0	0
T14	0	22	0	0
T15	0	11	0	0
T16	0	29	0	0
T17	0	36	0	0
T18	0	47	0	0
T19	0	5	0	0
T20	0	15	0	0
T21	0	37	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1621	0	0
T11	146984	17	0	0
T12	195963	0	0	0
T13	0	14	0	0
T14	0	31	0	0
T15	0	27	0	0
T16	0	27	0	0
T17	0	18	0	0
T18	0	42	0	0
T19	0	6	0	0
T20	0	23	0	0
T21	0	19	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1541	0	0
T11	146984	16	0	0
T12	195963	0	0	0
T13	0	18	0	0
T14	0	37	0	0
T15	0	19	0	0
T16	0	30	0	0
T17	0	20	0	0
T18	0	24	0	0
T19	0	9	0	0
T20	0	14	0	0
T21	0	38	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1424	0	0
T11	146984	5	0	0
T12	195963	0	0	0
T13	0	26	0	0
T14	0	16	0	0
T15	0	29	0	0
T16	0	31	0	0
T17	0	16	0	0
T18	0	33	0	0
T19	0	14	0	0
T20	0	17	0	0
T21	0	37	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1491	0	0
T11	146984	1	0	0
T12	195963	0	0	0
T13	0	28	0	0
T14	0	24	0	0
T15	0	21	0	0
T16	0	43	0	0
T17	0	16	0	0
T18	0	46	0	0
T19	0	4	0	0
T20	0	24	0	0
T21	0	29	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1279	0	0
T11	146984	11	0	0
T12	195963	0	0	0
T13	0	18	0	0
T14	0	12	0	0
T15	0	19	0	0
T16	0	17	0	0
T17	0	23	0	0
T18	0	33	0	0
T19	0	13	0	0
T20	0	14	0	0
T21	0	31	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1353	0	0
T11	146984	13	0	0
T12	195963	0	0	0
T13	0	17	0	0
T14	0	26	0	0
T15	0	22	0	0
T16	0	32	0	0
T17	0	20	0	0
T18	0	32	0	0
T19	0	6	0	0
T20	0	22	0	0
T21	0	32	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1342	0	0
T11	146984	20	0	0
T12	195963	0	0	0
T13	0	22	0	0
T14	0	18	0	0
T15	0	14	0	0
T16	0	30	0	0
T17	0	25	0	0
T18	0	52	0	0
T19	0	20	0	0
T20	0	18	0	0
T21	0	22	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1406	0	0
T11	146984	4	0	0
T12	195963	0	0	0
T13	0	21	0	0
T14	0	24	0	0
T15	0	4	0	0
T16	0	29	0	0
T17	0	12	0	0
T18	0	35	0	0
T19	0	18	0	0
T20	0	16	0	0
T21	0	40	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1347	0	0
T11	146984	16	0	0
T12	195963	0	0	0
T13	0	11	0	0
T14	0	33	0	0
T15	0	23	0	0
T16	0	24	0	0
T17	0	16	0	0
T18	0	39	0	0
T19	0	6	0	0
T20	0	15	0	0
T21	0	24	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1335	0	0
T11	146984	20	0	0
T12	195963	0	0	0
T13	0	21	0	0
T14	0	23	0	0
T15	0	19	0	0
T16	0	37	0	0
T17	0	17	0	0
T18	0	40	0	0
T19	0	10	0	0
T20	0	22	0	0
T21	0	34	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T11	146984	8	0	0
T12	195963	0	0	0
T13	0	3	0	0
T14	0	35	0	0
T15	0	20	0	0
T16	0	29	0	0
T17	0	12	0	0
T18	0	40	0	0
T19	0	17	0	0
T20	0	20	0	0
T21	0	21	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1625	0	0
T11	146984	38	0	0
T12	195963	0	0	0
T13	0	15	0	0
T14	0	25	0	0
T15	0	17	0	0
T16	0	57	0	0
T17	0	30	0	0
T22	118511	0	0	0
T23	322751	0	0	0
T24	245187	0	0	0
T25	411990	0	0	0
T26	169931	0	0	0
T27	177288	0	0	0
T28	604376	0	0	0
T29	443832	0	0	0
T30	0	19	0	0
T31	0	14	0	0
T32	0	2	0	0
T33	0	19	0	0