Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1200173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1174926

1

T1

19

T2

4142

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2089178	1			T2	7916		T4	2483		T5	4935
values[0x0]	142813	1			T1	16		T2	278		T3	32
values[0x1]	143108	1			T1	21		T2	276		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	960995	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1414104

1

T1

21

T2

4991

T3

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6528	1			T1	1		T2	22		T5	4
valid_sources[0x01]	12333	1			T2	27		T5	2		T6	4362
valid_sources[0x02]	7482	1			T2	32		T5	14		T6	15
valid_sources[0x03]	6953	1			T2	34		T5	23		T6	22
valid_sources[0x04]	7062	1			T2	32		T5	10		T6	26
valid_sources[0x05]	7934	1			T2	53		T5	18		T6	11
valid_sources[0x06]	6814	1			T2	27		T5	13		T6	11
valid_sources[0x07]	7411	1			T2	24		T5	24		T6	21
valid_sources[0x08]	6509	1			T2	28		T5	5		T6	34
valid_sources[0x09]	8097	1			T2	51		T5	34		T6	19
valid_sources[0x0a]	9576	1			T2	27		T5	2		T6	21
valid_sources[0x0b]	6949	1			T2	27		T5	22		T6	25
valid_sources[0x0c]	17704	1			T2	45		T5	18		T6	9
valid_sources[0x0d]	7267	1			T1	1		T2	16		T5	25
valid_sources[0x0e]	8761	1			T2	35		T6	19		T8	3
valid_sources[0x0f]	9002	1			T2	42		T5	4		T6	18
valid_sources[0x10]	7129	1			T2	37		T5	11		T6	25
valid_sources[0x11]	6983	1			T2	41		T5	3		T6	16
valid_sources[0x12]	8992	1			T1	1		T2	27		T5	10
valid_sources[0x13]	8278	1			T2	32		T5	27		T6	25
valid_sources[0x14]	7181	1			T2	22		T5	4		T6	21
valid_sources[0x15]	8322	1			T2	46		T5	30		T6	15
valid_sources[0x16]	13284	1			T2	22		T5	8		T6	18
valid_sources[0x17]	14002	1			T2	32		T5	9		T6	24
valid_sources[0x18]	7024	1			T2	22		T5	24		T6	21
valid_sources[0x19]	11033	1			T2	19		T5	14		T6	16
valid_sources[0x1a]	8869	1			T2	20		T6	17		T8	3
valid_sources[0x1b]	11902	1			T2	35		T5	6		T6	10
valid_sources[0x1c]	7201	1			T2	27		T5	7		T6	14
valid_sources[0x1d]	7144	1			T2	31		T5	7		T6	21
valid_sources[0x1e]	11613	1			T2	56		T5	18		T6	13
valid_sources[0x1f]	6768	1			T2	39		T5	10		T6	18
valid_sources[0x20]	7172	1			T2	26		T5	15		T6	28
valid_sources[0x21]	6833	1			T2	27		T5	7		T6	16
valid_sources[0x22]	6791	1			T2	24		T5	13		T6	13
valid_sources[0x23]	8200	1			T2	37		T5	12		T6	17
valid_sources[0x24]	7053	1			T2	28		T5	16		T6	12
valid_sources[0x25]	7064	1			T2	33		T5	14		T6	14
valid_sources[0x26]	7225	1			T1	5		T2	33		T5	4
valid_sources[0x27]	6631	1			T2	27		T5	18		T6	13
valid_sources[0x28]	7252	1			T2	37		T5	19		T6	22
valid_sources[0x29]	11914	1			T2	61		T5	2		T6	19
valid_sources[0x2a]	7196	1			T2	48		T5	8		T6	21
valid_sources[0x2b]	7770	1			T2	32		T5	27		T6	13
valid_sources[0x2c]	11473	1			T2	29		T5	25		T6	22
valid_sources[0x2d]	10256	1			T2	48		T5	17		T6	30
valid_sources[0x2e]	6633	1			T2	33		T6	31		T8	5
valid_sources[0x2f]	7570	1			T2	31		T5	14		T6	12
valid_sources[0x30]	7990	1			T2	35		T5	12		T6	15
valid_sources[0x31]	7846	1			T1	3		T2	38		T6	17
valid_sources[0x32]	7249	1			T2	36		T5	6		T6	20
valid_sources[0x33]	7668	1			T2	45		T5	1		T6	5
valid_sources[0x34]	11209	1			T2	35		T5	13		T6	6
valid_sources[0x35]	7152	1			T2	23		T5	8		T6	15
valid_sources[0x36]	7938	1			T2	32		T5	4		T6	23
valid_sources[0x37]	6679	1			T2	35		T5	3		T6	24
valid_sources[0x38]	7721	1			T2	38		T5	7		T6	20
valid_sources[0x39]	7776	1			T2	41		T5	9		T6	13
valid_sources[0x3a]	21465	1			T2	67		T5	32		T6	17
valid_sources[0x3b]	7355	1			T2	55		T5	10		T6	19
valid_sources[0x3c]	8418	1			T2	40		T3	7		T5	3
valid_sources[0x3d]	6536	1			T2	44		T5	1		T6	10
valid_sources[0x3e]	6745	1			T2	26		T5	5		T6	12
valid_sources[0x3f]	7684	1			T2	17		T5	11		T6	16
valid_sources[0x40]	6629	1			T2	29		T5	29		T6	37
valid_sources[0x41]	7089	1			T2	34		T3	5		T5	16
valid_sources[0x42]	19987	1			T2	46		T5	22		T6	20
valid_sources[0x43]	6888	1			T2	38		T5	13		T6	27
valid_sources[0x44]	7011	1			T2	18		T5	6		T6	10
valid_sources[0x45]	6856	1			T1	1		T2	23		T5	41
valid_sources[0x46]	7012	1			T2	43		T5	17		T6	29
valid_sources[0x47]	15714	1			T2	54		T5	15		T6	22
valid_sources[0x48]	6919	1			T2	33		T6	10		T8	4
valid_sources[0x49]	7401	1			T2	36		T5	2		T6	28
valid_sources[0x4a]	7950	1			T2	38		T5	2		T6	23
valid_sources[0x4b]	12110	1			T2	32		T5	38		T6	18
valid_sources[0x4c]	7496	1			T2	33		T5	2		T6	18
valid_sources[0x4d]	6842	1			T2	39		T5	13		T6	13
valid_sources[0x4e]	7382	1			T2	20		T6	19		T7	49
valid_sources[0x4f]	9096	1			T2	24		T5	11		T6	11
valid_sources[0x50]	7372	1			T2	25		T5	11		T6	8
valid_sources[0x51]	11580	1			T2	42		T5	28		T6	22
valid_sources[0x52]	7052	1			T2	17		T5	14		T6	14
valid_sources[0x53]	7615	1			T2	31		T5	11		T6	18
valid_sources[0x54]	10066	1			T2	32		T3	3		T5	1
valid_sources[0x55]	15678	1			T2	42		T5	10		T6	5
valid_sources[0x56]	10554	1			T2	22		T5	3		T6	27
valid_sources[0x57]	8902	1			T2	31		T5	10		T6	14
valid_sources[0x58]	7135	1			T2	43		T5	8		T6	17
valid_sources[0x59]	8270	1			T2	30		T5	10		T6	25
valid_sources[0x5a]	8504	1			T1	1		T2	44		T6	20
valid_sources[0x5b]	6946	1			T2	30		T5	10		T6	21
valid_sources[0x5c]	23856	1			T2	36		T5	13		T6	17
valid_sources[0x5d]	6891	1			T2	30		T5	14		T6	16
valid_sources[0x5e]	9199	1			T2	20		T5	2		T6	16
valid_sources[0x5f]	7064	1			T2	43		T5	5		T6	11
valid_sources[0x60]	7371	1			T2	44		T3	2		T5	10
valid_sources[0x61]	7037	1			T2	48		T5	3		T6	25
valid_sources[0x62]	11350	1			T1	1		T2	27		T5	27
valid_sources[0x63]	7418	1			T2	38		T6	30		T8	5
valid_sources[0x64]	12374	1			T2	32		T5	7		T6	17
valid_sources[0x65]	9846	1			T2	49		T5	25		T6	24
valid_sources[0x66]	8982	1			T2	29		T6	11		T8	5
valid_sources[0x67]	6734	1			T2	46		T5	4		T6	15
valid_sources[0x68]	11499	1			T2	31		T5	8		T6	25
valid_sources[0x69]	7201	1			T2	33		T5	6		T6	29
valid_sources[0x6a]	6735	1			T2	38		T6	27		T8	3
valid_sources[0x6b]	16304	1			T2	38		T5	29		T6	12
valid_sources[0x6c]	8357	1			T2	38		T5	5		T6	20
valid_sources[0x6d]	6871	1			T1	2		T2	38		T5	3
valid_sources[0x6e]	6746	1			T2	36		T5	8		T6	36
valid_sources[0x6f]	7209	1			T2	24		T5	38		T6	17
valid_sources[0x70]	7283	1			T1	1		T2	43		T5	4
valid_sources[0x71]	8267	1			T2	29		T5	6		T6	22
valid_sources[0x72]	9799	1			T1	2		T2	47		T5	4
valid_sources[0x73]	10497	1			T2	35		T5	6		T6	14
valid_sources[0x74]	7379	1			T1	2		T2	43		T5	15
valid_sources[0x75]	7398	1			T2	30		T5	2		T6	10
valid_sources[0x76]	7902	1			T2	27		T5	12		T6	13
valid_sources[0x77]	6915	1			T2	38		T5	20		T6	5
valid_sources[0x78]	8226	1			T2	36		T3	3		T5	1
valid_sources[0x79]	7945	1			T1	4		T2	27		T5	8
valid_sources[0x7a]	7380	1			T2	36		T5	9		T6	24
valid_sources[0x7b]	6995	1			T1	1		T2	35		T5	13
valid_sources[0x7c]	7247	1			T2	46		T5	3		T6	12
valid_sources[0x7d]	8127	1			T2	36		T5	4		T6	10
valid_sources[0x7e]	6842	1			T2	35		T5	8		T6	29
valid_sources[0x7f]	6792	1			T2	34		T5	7		T6	9
valid_sources[0x80]	8334	1			T2	27		T5	4		T6	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1039582

1

T2

3936

T4

1237

T5

2450

values[0x0]

all_enables

biggest_size

78617

1

T1

9

T2

134

T3

18

values[0x1]

all_enables

biggest_size

56727

1

T1

10

T2

72

T3

11