Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28040	1			T2	14		T4	6		T5	11
auto[PWRUP]	98	1			T55	4		T38	1		T40	1
auto[ONEST_0]	69	1			T54	2		T43	1		T57	2
auto[ONEST_021]	16	1			T54	1		T43	1		T201	1
auto[ONEST_1]	73	1			T8	2		T55	1		T58	1
auto[ONEST_DONE]	5	1			T202	1		T203	1		T204	1
auto[LP_0]	116	1			T43	1		T58	2		T37	1
auto[LP_021]	30	1			T8	2		T54	1		T55	2
auto[LP_1]	108	1			T8	4		T55	2		T43	1
auto[LP_EVAL]	51	1			T8	1		T54	1		T58	1
auto[LP_SLP]	420	1			T8	4		T54	3		T55	7
auto[LP_PWRUP]	27	1			T55	1		T43	1		T205	1
auto[NP_0]	143	1			T8	2		T54	2		T55	2
auto[NP_021]	42	1			T8	1		T54	1		T43	1
auto[NP_1]	158	1			T8	3		T54	4		T55	2
auto[NP_EVAL]	20	1			T56	1		T206	2		T207	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T208

1

T209

1

T210

1

min

27550

1

T2

14

T4

6

T5

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27563	1			T2	14		T4	6		T5	11
pow[0x1]	13	1			T205	1		T17	1		T211	2
pow[0x2]	13	1			T202	1		T212	1		T211	2
pow[0x3]	41	1			T57	1		T86	1		T56	3
pow[0x4]	73	1			T8	2		T12	1		T54	2
pow[0x5]	116	1			T8	1		T54	4		T55	2
pow[0x6]	218	1			T54	3		T55	3		T43	2
pow[0x7]	478	1			T8	10		T54	4		T55	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

176

1

T8

1

T12

1

T54

5

min

27163

1

T2

14

T4

6

T5

11

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27163	1			T2	14		T4	6		T5	11
pow[0x3]	1	1			T213	1		-	-		-	-
pow[0x5]	1	1			T214	1		-	-		-	-
pow[0x7]	1	1			T215	1		-	-		-	-
pow[0x8]	3	1			T202	1		T216	1		T217	1
pow[0x9]	11	1			T57	1		T218	1		T219	1
pow[0xa]	13	1			T220	1		T221	1		T214	1
pow[0xb]	21	1			T37	1		T57	1		T86	1
pow[0xc]	65	1			T54	1		T55	1		T43	1
pow[0xd]	150	1			T8	1		T54	3		T55	3
pow[0xe]	256	1			T8	6		T54	2		T55	5
pow[0xf]	522	1			T8	9		T54	4		T55	4