Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2178	1			T8	21		T9	4		T11	3
auto[PWRUP]	103	1			T8	2		T54	1		T55	2
auto[ONEST_0]	84	1			T8	2		T15	1		T54	3
auto[ONEST_021]	11	1			T57	1		T265	2		T352	1
auto[ONEST_1]	84	1			T8	1		T58	1		T37	1
auto[ONEST_DONE]	6	1			T15	1		T57	1		T229	1
auto[LP_0]	125	1			T8	2		T54	2		T55	1
auto[LP_021]	30	1			T8	1		T39	1		T206	1
auto[LP_1]	103	1			T8	2		T54	1		T55	2
auto[LP_EVAL]	43	1			T55	1		T43	1		T58	1
auto[LP_SLP]	469	1			T8	3		T54	4		T55	9
auto[LP_PWRUP]	30	1			T54	1		T86	1		T207	1
auto[NP_0]	219	1			T8	3		T12	1		T54	1
auto[NP_021]	49	1			T8	1		T54	2		T43	1
auto[NP_1]	179	1			T8	2		T54	3		T55	1
auto[NP_EVAL]	29	1			T39	1		T49	1		T56	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T205

2

T49

1

T218

1

min

1888

1

T8

4

T9

4

T11

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1902	1			T8	4		T9	4		T11	3
pow[0x1]	12	1			T8	1		T353	1		T354	1
pow[0x2]	14	1			T55	1		T221	1		T218	1
pow[0x3]	34	1			T8	1		T16	1		T40	1
pow[0x4]	53	1			T54	1		T55	1		T43	1
pow[0x5]	116	1			T8	1		T54	1		T55	3
pow[0x6]	245	1			T8	5		T54	4		T55	4
pow[0x7]	455	1			T8	8		T54	6		T55	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

164

1

T8

3

T54

2

T55

3

min

1354

1

T8

2

T9

4

T11

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1361	1			T8	2		T9	4		T11	3
pow[0x1]	11	1			T229	1		T218	2		T298	4
pow[0x2]	31	1			T37	1		T39	4		T18	1
pow[0x3]	35	1			T37	1		T40	2		T49	1
pow[0x4]	58	1			T12	1		T35	1		T37	2
pow[0x5]	1	1			T355	1		-	-		-	-
pow[0x7]	1	1			T43	1		-	-		-	-
pow[0x8]	5	1			T54	1		T218	1		T211	1
pow[0x9]	4	1			T8	2		T205	1		T221	1
pow[0xa]	17	1			T54	1		T43	1		T58	1
pow[0xb]	37	1			T8	2		T55	3		T58	1
pow[0xc]	72	1			T54	2		T43	1		T58	3
pow[0xd]	140	1			T8	1		T54	4		T37	1
pow[0xe]	263	1			T8	5		T54	2		T55	3
pow[0xf]	542	1			T8	10		T12	1		T54	6