Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1225	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1365	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1288	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1215	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1260	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1287	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1334	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1354	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1351	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1372	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1267	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1322	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1284	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1287	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1285	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1263	0	0
adc_en_ctl_rd_A	2147483647	1079	0	0
adc_fsm_rst_rd_A	2147483647	837	0	0
adc_intr_ctl_rd_A	2147483647	1304	0	0
adc_lp_sample_ctl_rd_A	2147483647	944	0	0
adc_pd_ctl_rd_A	2147483647	1277	0	0
adc_sample_ctl_rd_A	2147483647	944	0	0
adc_wakeup_ctl_rd_A	2147483647	1012	0	0
intr_enable_rd_A	2147483647	1571	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1225	0	0
T12	126331	4	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	13	0	0
T16	0	28	0	0
T17	0	26	0	0
T18	0	18	0	0
T19	0	10	0	0
T20	0	13	0	0
T21	0	26	0	0
T22	0	17	0	0
T23	0	7	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1365	0	0
T12	126331	17	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	5	0	0
T16	0	15	0	0
T17	0	15	0	0
T18	0	26	0	0
T19	0	22	0	0
T20	0	13	0	0
T21	0	21	0	0
T22	0	4	0	0
T23	0	7	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1288	0	0
T12	126331	17	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	2	0	0
T16	0	18	0	0
T17	0	33	0	0
T18	0	11	0	0
T19	0	24	0	0
T20	0	16	0	0
T21	0	8	0	0
T22	0	22	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0
T31	0	11	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1215	0	0
T12	126331	17	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	25	0	0
T16	0	11	0	0
T17	0	26	0	0
T18	0	29	0	0
T19	0	18	0	0
T20	0	14	0	0
T21	0	15	0	0
T22	0	16	0	0
T23	0	4	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1260	0	0
T12	126331	3	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	10	0	0
T16	0	18	0	0
T17	0	7	0	0
T18	0	12	0	0
T19	0	21	0	0
T20	0	7	0	0
T21	0	9	0	0
T22	0	3	0	0
T23	0	6	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1287	0	0
T12	126331	17	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	8	0	0
T16	0	26	0	0
T17	0	26	0	0
T18	0	15	0	0
T19	0	19	0	0
T20	0	7	0	0
T21	0	13	0	0
T22	0	16	0	0
T23	0	2	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1334	0	0
T12	126331	23	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	1	0	0
T16	0	25	0	0
T17	0	24	0	0
T18	0	8	0	0
T19	0	18	0	0
T20	0	5	0	0
T21	0	11	0	0
T22	0	19	0	0
T23	0	11	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1354	0	0
T12	126331	6	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	6	0	0
T16	0	27	0	0
T17	0	20	0	0
T18	0	16	0	0
T19	0	21	0	0
T20	0	19	0	0
T21	0	14	0	0
T22	0	35	0	0
T23	0	9	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1351	0	0
T12	126331	11	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T16	0	17	0	0
T17	0	30	0	0
T18	0	23	0	0
T19	0	11	0	0
T20	0	1	0	0
T21	0	26	0	0
T22	0	17	0	0
T23	0	9	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0
T31	0	7	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T12	126331	4	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	12	0	0
T16	0	17	0	0
T17	0	23	0	0
T18	0	17	0	0
T19	0	15	0	0
T20	0	6	0	0
T21	0	19	0	0
T22	0	29	0	0
T23	0	6	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1267	0	0
T12	126331	14	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	9	0	0
T16	0	12	0	0
T17	0	32	0	0
T18	0	18	0	0
T19	0	16	0	0
T20	0	12	0	0
T21	0	3	0	0
T22	0	27	0	0
T23	0	21	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1322	0	0
T12	126331	13	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T16	0	29	0	0
T17	0	43	0	0
T18	0	14	0	0
T19	0	21	0	0
T20	0	9	0	0
T21	0	10	0	0
T22	0	24	0	0
T23	0	13	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0
T31	0	13	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1284	0	0
T12	126331	11	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	19	0	0
T16	0	19	0	0
T17	0	36	0	0
T18	0	25	0	0
T19	0	7	0	0
T20	0	9	0	0
T21	0	8	0	0
T22	0	20	0	0
T23	0	6	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1287	0	0
T12	126331	7	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	13	0	0
T16	0	12	0	0
T17	0	28	0	0
T18	0	18	0	0
T19	0	29	0	0
T20	0	3	0	0
T21	0	24	0	0
T22	0	32	0	0
T23	0	21	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1285	0	0
T12	126331	13	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	3	0	0
T16	0	5	0	0
T17	0	24	0	0
T18	0	11	0	0
T19	0	21	0	0
T20	0	5	0	0
T21	0	19	0	0
T22	0	7	0	0
T23	0	3	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1263	0	0
T12	126331	6	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	8	0	0
T16	0	25	0	0
T17	0	35	0	0
T18	0	30	0	0
T19	0	15	0	0
T20	0	12	0	0
T21	0	28	0	0
T22	0	18	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0
T31	0	13	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1079	0	0
T12	126331	11	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	14	0	0
T16	0	24	0	0
T17	0	24	0	0
T18	0	28	0	0
T19	0	29	0	0
T20	0	16	0	0
T21	0	22	0	0
T22	0	20	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0
T31	0	5	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	837	0	0
T12	126331	12	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	8	0	0
T16	0	28	0	0
T17	0	43	0	0
T18	0	18	0	0
T19	0	26	0	0
T20	0	7	0	0
T21	0	18	0	0
T22	0	16	0	0
T23	0	7	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1304	0	0
T12	126331	12	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	9	0	0
T16	0	28	0	0
T17	0	42	0	0
T18	0	30	0	0
T19	0	18	0	0
T20	0	6	0	0
T21	0	9	0	0
T22	0	24	0	0
T23	0	11	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	944	0	0
T12	126331	10	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	15	0	0
T16	0	12	0	0
T17	0	25	0	0
T18	0	21	0	0
T19	0	18	0	0
T20	0	8	0	0
T21	0	12	0	0
T22	0	21	0	0
T23	0	8	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1277	0	0
T12	126331	15	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	4	0	0
T16	0	4	0	0
T17	0	21	0	0
T18	0	23	0	0
T19	0	11	0	0
T20	0	7	0	0
T21	0	18	0	0
T22	0	26	0	0
T23	0	7	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	944	0	0
T12	126331	8	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	11	0	0
T16	0	19	0	0
T17	0	35	0	0
T18	0	19	0	0
T19	0	32	0	0
T20	0	9	0	0
T21	0	6	0	0
T22	0	18	0	0
T23	0	2	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1012	0	0
T12	126331	6	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	3	0	0
T16	0	15	0	0
T17	0	33	0	0
T18	0	27	0	0
T19	0	14	0	0
T20	0	5	0	0
T21	0	24	0	0
T22	0	15	0	0
T23	0	16	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1571	0	0
T12	126331	89	0	0
T13	300867	0	0	0
T14	153405	0	0	0
T15	0	10	0	0
T16	0	19	0	0
T17	0	57	0	0
T18	0	22	0	0
T19	0	53	0	0
T20	0	12	0	0
T24	404150	0	0	0
T25	222834	0	0	0
T26	480654	0	0	0
T27	589401	0	0	0
T28	148247	0	0	0
T29	166020	0	0	0
T30	240099	0	0	0
T32	0	32	0	0
T33	0	4	0	0
T34	0	22	0	0