Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1199221	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1175865

1

T1

6398

T2

6451

T3

351

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2079361	1			T1	12135		T2	12286		T4	7270
values[0x0]	147709	1			T1	372		T2	371		T3	414
values[0x1]	148016	1			T1	393		T2	358		T3	467

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	960028	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1415058

1

T1

7671

T2

7790

T3

433

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6930	1			T1	72		T2	18		T3	8
valid_sources[0x01]	16489	1			T1	50		T2	24		T3	16
valid_sources[0x02]	6889	1			T1	36		T2	9		T4	10
valid_sources[0x03]	11028	1			T1	69		T2	36		T4	7
valid_sources[0x04]	10406	1			T1	49		T2	37		T3	2
valid_sources[0x05]	6354	1			T1	23		T2	53		T3	3
valid_sources[0x06]	9387	1			T1	61		T2	15		T3	3
valid_sources[0x07]	11912	1			T1	56		T2	40		T3	4
valid_sources[0x08]	7530	1			T1	26		T2	19		T3	2
valid_sources[0x09]	8397	1			T1	39		T2	22		T3	10
valid_sources[0x0a]	9728	1			T1	65		T2	18		T3	4
valid_sources[0x0b]	6899	1			T1	58		T2	44		T3	6
valid_sources[0x0c]	6701	1			T1	66		T2	43		T3	5
valid_sources[0x0d]	22686	1			T1	55		T2	17		T3	4
valid_sources[0x0e]	11317	1			T1	45		T2	89		T4	20
valid_sources[0x0f]	7807	1			T1	65		T2	18		T4	7
valid_sources[0x10]	9458	1			T1	54		T2	35		T3	1
valid_sources[0x11]	11593	1			T1	47		T2	14		T4	7
valid_sources[0x12]	14020	1			T1	27		T2	45		T3	5
valid_sources[0x13]	6679	1			T1	42		T2	36		T3	7
valid_sources[0x14]	20212	1			T1	63		T2	17		T4	12
valid_sources[0x15]	6992	1			T1	61		T2	11		T4	10
valid_sources[0x16]	7576	1			T1	50		T2	25		T3	2
valid_sources[0x17]	10992	1			T1	56		T2	41		T3	1
valid_sources[0x18]	6573	1			T1	42		T2	19		T3	7
valid_sources[0x19]	10025	1			T1	62		T2	26		T4	12
valid_sources[0x1a]	17534	1			T1	33		T2	16		T3	2
valid_sources[0x1b]	6999	1			T1	47		T2	28		T3	5
valid_sources[0x1c]	7348	1			T1	87		T2	35		T3	8
valid_sources[0x1d]	7398	1			T1	67		T2	48		T4	15
valid_sources[0x1e]	6571	1			T1	63		T2	16		T3	3
valid_sources[0x1f]	6741	1			T1	41		T2	38		T3	3
valid_sources[0x20]	6980	1			T1	63		T2	16		T4	7
valid_sources[0x21]	7048	1			T1	51		T2	33		T3	6
valid_sources[0x22]	6638	1			T1	58		T2	50		T3	2
valid_sources[0x23]	6438	1			T1	50		T2	16		T3	1
valid_sources[0x24]	6965	1			T1	75		T2	24		T4	8
valid_sources[0x25]	6986	1			T1	53		T2	35		T4	6
valid_sources[0x26]	6698	1			T1	52		T2	16		T3	4
valid_sources[0x27]	11769	1			T1	80		T2	25		T3	15
valid_sources[0x28]	8582	1			T1	40		T2	35		T3	5
valid_sources[0x29]	6781	1			T1	89		T2	32		T3	8
valid_sources[0x2a]	7785	1			T1	47		T2	25		T3	2
valid_sources[0x2b]	6978	1			T1	34		T2	15		T4	6
valid_sources[0x2c]	15942	1			T1	46		T2	20		T3	3
valid_sources[0x2d]	6770	1			T1	31		T2	85		T3	5
valid_sources[0x2e]	11058	1			T1	36		T2	20		T3	6
valid_sources[0x2f]	10606	1			T1	56		T2	32		T3	7
valid_sources[0x30]	6753	1			T1	41		T2	10		T4	11
valid_sources[0x31]	11525	1			T1	70		T2	4336		T3	4
valid_sources[0x32]	10900	1			T1	49		T2	33		T3	3
valid_sources[0x33]	7087	1			T1	58		T2	30		T3	2
valid_sources[0x34]	6489	1			T1	55		T2	55		T3	8
valid_sources[0x35]	9734	1			T1	45		T2	41		T3	9
valid_sources[0x36]	6794	1			T1	44		T2	28		T3	2
valid_sources[0x37]	8280	1			T1	43		T2	25		T4	10
valid_sources[0x38]	7130	1			T1	47		T2	39		T3	1
valid_sources[0x39]	17583	1			T1	22		T2	43		T4	5
valid_sources[0x3a]	6243	1			T1	51		T2	44		T3	3
valid_sources[0x3b]	10900	1			T1	36		T2	18		T3	4
valid_sources[0x3c]	7427	1			T1	45		T2	25		T3	6
valid_sources[0x3d]	6780	1			T1	41		T2	13		T4	15
valid_sources[0x3e]	7423	1			T1	28		T2	9		T3	2
valid_sources[0x3f]	12245	1			T1	43		T2	42		T3	4
valid_sources[0x40]	7129	1			T1	66		T2	50		T4	4
valid_sources[0x41]	7679	1			T1	34		T2	34		T3	13
valid_sources[0x42]	6842	1			T1	84		T2	33		T3	3
valid_sources[0x43]	6990	1			T1	55		T2	47		T3	3
valid_sources[0x44]	6844	1			T1	58		T2	19		T3	3
valid_sources[0x45]	9926	1			T1	60		T2	29		T3	4
valid_sources[0x46]	16545	1			T1	61		T2	68		T3	1
valid_sources[0x47]	7160	1			T1	72		T2	48		T3	1
valid_sources[0x48]	7561	1			T1	51		T2	12		T3	15
valid_sources[0x49]	9221	1			T1	81		T2	82		T4	7
valid_sources[0x4a]	10192	1			T1	49		T2	30		T3	6
valid_sources[0x4b]	6406	1			T1	56		T2	20		T3	1
valid_sources[0x4c]	7204	1			T1	42		T2	52		T3	1
valid_sources[0x4d]	7128	1			T1	33		T2	26		T4	4
valid_sources[0x4e]	6583	1			T1	50		T2	23		T3	8
valid_sources[0x4f]	7152	1			T1	69		T2	10		T3	6
valid_sources[0x50]	6539	1			T1	31		T2	15		T3	1
valid_sources[0x51]	11782	1			T1	66		T2	63		T4	12
valid_sources[0x52]	14363	1			T1	39		T2	28		T3	2
valid_sources[0x53]	9085	1			T1	47		T2	45		T4	8
valid_sources[0x54]	6419	1			T1	36		T2	20		T4	8
valid_sources[0x55]	7560	1			T1	53		T2	31		T3	6
valid_sources[0x56]	6829	1			T1	45		T2	23		T4	14
valid_sources[0x57]	6821	1			T1	76		T2	19		T3	10
valid_sources[0x58]	7998	1			T1	48		T2	28		T4	8
valid_sources[0x59]	10784	1			T1	52		T2	26		T3	8
valid_sources[0x5a]	6950	1			T1	39		T2	49		T3	14
valid_sources[0x5b]	6662	1			T1	65		T2	18		T4	14
valid_sources[0x5c]	10556	1			T1	45		T2	26		T3	1
valid_sources[0x5d]	6766	1			T1	38		T2	19		T3	2
valid_sources[0x5e]	28051	1			T1	63		T2	15		T4	10
valid_sources[0x5f]	6967	1			T1	38		T2	47		T3	9
valid_sources[0x60]	6811	1			T1	75		T2	46		T3	3
valid_sources[0x61]	12864	1			T1	38		T2	11		T3	7
valid_sources[0x62]	6750	1			T1	43		T2	29		T3	9
valid_sources[0x63]	16609	1			T1	31		T2	49		T3	7
valid_sources[0x64]	6916	1			T1	33		T2	36		T3	2
valid_sources[0x65]	6631	1			T1	39		T2	42		T3	1
valid_sources[0x66]	8596	1			T1	81		T2	44		T3	3
valid_sources[0x67]	6997	1			T1	22		T2	30		T4	13
valid_sources[0x68]	7133	1			T1	48		T2	40		T4	8
valid_sources[0x69]	12912	1			T1	36		T2	59		T3	3
valid_sources[0x6a]	9547	1			T1	66		T2	17		T3	8
valid_sources[0x6b]	7541	1			T1	42		T2	70		T4	7
valid_sources[0x6c]	10969	1			T1	41		T2	15		T3	2
valid_sources[0x6d]	10743	1			T1	55		T2	18		T3	1
valid_sources[0x6e]	12580	1			T1	56		T2	27		T3	3
valid_sources[0x6f]	6319	1			T1	37		T2	36		T3	1
valid_sources[0x70]	6740	1			T1	45		T2	34		T3	8
valid_sources[0x71]	12175	1			T1	39		T2	70		T3	1
valid_sources[0x72]	6974	1			T1	53		T2	51		T3	4
valid_sources[0x73]	9355	1			T1	53		T2	39		T3	1
valid_sources[0x74]	6462	1			T1	29		T2	89		T3	4
valid_sources[0x75]	6418	1			T1	58		T2	42		T3	2
valid_sources[0x76]	7302	1			T1	61		T2	22		T3	14
valid_sources[0x77]	7062	1			T1	55		T2	32		T3	2
valid_sources[0x78]	10021	1			T1	42		T2	73		T3	17
valid_sources[0x79]	10436	1			T1	47		T2	49		T4	13
valid_sources[0x7a]	8332	1			T1	43		T2	60		T3	4
valid_sources[0x7b]	7886	1			T1	71		T2	15		T4	22
valid_sources[0x7c]	6854	1			T1	45		T2	77		T4	17
valid_sources[0x7d]	7284	1			T1	55		T2	14		T3	1
valid_sources[0x7e]	14026	1			T1	44		T2	14		T4	17
valid_sources[0x7f]	6799	1			T1	69		T2	40		T3	2
valid_sources[0x80]	12377	1			T1	55		T2	19		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1036740

1

T1

6094

T2

6170

T4

3592

values[0x0]

all_enables

biggest_size

80768

1

T1

189

T2

181

T3

199

values[0x1]

all_enables

biggest_size

58357

1

T1

115

T2

100

T3

152