Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30418	1			T1	23		T2	20		T3	268
auto[PWRUP]	112	1			T3	2		T53	2		T63	1
auto[ONEST_0]	53	1			T53	2		T24	1		T197	1
auto[ONEST_021]	21	1			T63	1		T62	1		T65	2
auto[ONEST_1]	61	1			T63	1		T198	1		T65	2
auto[ONEST_DONE]	3	1			T62	1		T198	1		T33	1
auto[LP_0]	107	1			T53	1		T63	2		T62	2
auto[LP_021]	34	1			T3	2		T63	1		T65	1
auto[LP_1]	119	1			T53	3		T63	1		T198	2
auto[LP_EVAL]	46	1			T3	1		T53	2		T199	1
auto[LP_SLP]	501	1			T3	9		T53	10		T63	6
auto[LP_PWRUP]	35	1			T65	1		T66	1		T200	5
auto[NP_0]	147	1			T3	2		T53	2		T63	2
auto[NP_021]	37	1			T3	1		T199	1		T200	2
auto[NP_1]	144	1			T3	4		T53	3		T62	2
auto[NP_EVAL]	36	1			T3	1		T63	1		T201	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T53

1

T63

1

T201

1

min

29893

1

T1

23

T2

20

T3

263

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29904	1			T1	23		T2	20		T3	263
pow[0x1]	4	1			T201	1		T202	1		T203	1
pow[0x2]	16	1			T3	1		T204	1		T205	2
pow[0x3]	24	1			T53	1		T198	2		T199	1
pow[0x4]	71	1			T63	2		T62	2		T198	3
pow[0x5]	149	1			T3	3		T53	2		T63	7
pow[0x6]	234	1			T3	1		T53	2		T63	3
pow[0x7]	486	1			T3	9		T53	6		T63	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

167

1

T3

1

T53

4

T63

3

min

29406

1

T1

23

T2

20

T3

255

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29406	1			T1	23		T2	20		T3	255
pow[0x6]	1	1			T206	1		-	-		-	-
pow[0x7]	1	1			T207	1		-	-		-	-
pow[0x8]	4	1			T208	1		T209	1		T210	1
pow[0x9]	4	1			T200	1		T211	1		T212	1
pow[0xa]	23	1			T66	1		T207	1		T213	2
pow[0xb]	25	1			T199	1		T66	3		T200	1
pow[0xc]	74	1			T3	1		T63	1		T198	1
pow[0xd]	143	1			T53	3		T63	2		T62	3
pow[0xe]	275	1			T3	6		T53	4		T63	1
pow[0xf]	556	1			T3	6		T53	8		T63	9