Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2284	1			T3	14		T44	11		T53	22
auto[PWRUP]	141	1			T3	3		T44	1		T63	1
auto[ONEST_0]	72	1			T53	2		T63	1		T62	1
auto[ONEST_021]	22	1			T3	1		T53	1		T45	1
auto[ONEST_1]	93	1			T3	1		T44	1		T53	1
auto[ONEST_DONE]	2	1			T205	1		T352	1		-	-
auto[LP_0]	123	1			T3	2		T53	2		T63	3
auto[LP_021]	32	1			T53	1		T63	1		T199	1
auto[LP_1]	146	1			T3	1		T63	4		T62	2
auto[LP_EVAL]	76	1			T3	1		T53	1		T62	1
auto[LP_SLP]	512	1			T3	7		T44	1		T53	7
auto[LP_PWRUP]	24	1			T63	2		T24	1		T201	1
auto[NP_0]	221	1			T3	3		T44	3		T53	3
auto[NP_021]	66	1			T63	1		T45	1		T62	1
auto[NP_1]	237	1			T3	1		T44	1		T53	3
auto[NP_EVAL]	34	1			T65	1		T49	2		T66	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T24

1

T353

1

T33

1

min

1965

1

T3

8

T44

18

T53

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1972	1			T3	8		T44	18		T53	10
pow[0x1]	14	1			T63	1		T65	1		T200	1
pow[0x2]	18	1			T3	1		T198	1		T65	1
pow[0x3]	32	1			T3	1		T53	1		T62	2
pow[0x4]	79	1			T63	1		T62	4		T198	1
pow[0x5]	119	1			T3	4		T53	2		T63	1
pow[0x6]	260	1			T3	3		T53	5		T63	5
pow[0x7]	544	1			T3	3		T53	8		T63	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

201

1

T3

5

T53

6

T63

3

min

1360

1

T3

1

T44

14

T53

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1370	1			T3	1		T44	14		T53	3
pow[0x1]	23	1			T44	1		T45	1		T48	1
pow[0x2]	22	1			T44	3		T13	1		T50	3
pow[0x3]	39	1			T45	1		T46	3		T47	2
pow[0x4]	60	1			T45	1		T48	2		T49	3
pow[0x7]	3	1			T197	1		T211	1		T354	1
pow[0x8]	3	1			T213	1		T355	1		T356	1
pow[0x9]	13	1			T63	1		T357	1		T208	1
pow[0xa]	16	1			T199	1		T200	1		T358	2
pow[0xb]	36	1			T3	2		T63	2		T201	2
pow[0xc]	80	1			T3	1		T53	1		T63	1
pow[0xd]	154	1			T3	2		T53	3		T63	1
pow[0xe]	300	1			T3	2		T53	6		T63	3
pow[0xf]	583	1			T3	5		T53	9		T63	11