Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1213873	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1187231

1

T1

32

T2

495

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2099660	1			T2	877		T13	1		T4	4202
values[0x0]	150256	1			T1	28		T2	63		T3	27
values[0x1]	151188	1			T1	33		T2	46		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	973686	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1427418

1

T1

39

T2

601

T3

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7060	1			T2	9		T4	42		T7	30
valid_sources[0x01]	7744	1			T2	1		T4	11		T7	48
valid_sources[0x02]	7181	1			T1	1		T2	6		T4	30
valid_sources[0x03]	7011	1			T4	26		T7	27		T9	7
valid_sources[0x04]	7019	1			T2	6		T4	23		T6	28
valid_sources[0x05]	11317	1			T2	5		T4	11		T7	30
valid_sources[0x06]	11078	1			T2	8		T4	21		T7	35
valid_sources[0x07]	8455	1			T4	20		T7	20		T9	13
valid_sources[0x08]	11223	1			T4	18		T7	26		T9	22
valid_sources[0x09]	7240	1			T1	3		T2	1		T4	13
valid_sources[0x0a]	11627	1			T1	1		T2	8		T4	16
valid_sources[0x0b]	9490	1			T2	6		T4	24		T6	7
valid_sources[0x0c]	6966	1			T2	2		T4	18		T6	13
valid_sources[0x0d]	7050	1			T2	1		T4	19		T6	9
valid_sources[0x0e]	11650	1			T4	19		T6	3		T7	14
valid_sources[0x0f]	7576	1			T4	10		T6	17		T7	24
valid_sources[0x10]	11847	1			T2	4		T4	5		T6	16
valid_sources[0x11]	6828	1			T2	1		T4	26		T7	16
valid_sources[0x12]	7356	1			T2	4		T4	16		T6	30
valid_sources[0x13]	7124	1			T1	1		T2	4		T4	12
valid_sources[0x14]	7900	1			T2	3		T4	12		T6	971
valid_sources[0x15]	7352	1			T2	4		T4	18		T6	3
valid_sources[0x16]	12391	1			T2	6		T4	10		T7	26
valid_sources[0x17]	7438	1			T2	7		T4	14		T6	9
valid_sources[0x18]	7704	1			T1	2		T2	2		T4	14
valid_sources[0x19]	7001	1			T2	5		T4	20		T7	43
valid_sources[0x1a]	11492	1			T2	3		T4	15		T7	30
valid_sources[0x1b]	6957	1			T2	9		T4	31		T6	11
valid_sources[0x1c]	8677	1			T2	3		T4	16		T7	44
valid_sources[0x1d]	6720	1			T2	1		T4	11		T7	27
valid_sources[0x1e]	7375	1			T2	3		T4	17		T6	11
valid_sources[0x1f]	7930	1			T2	3		T4	30		T7	20
valid_sources[0x20]	17116	1			T2	2		T4	31		T7	32
valid_sources[0x21]	7957	1			T2	2		T4	13		T6	2
valid_sources[0x22]	13830	1			T4	17		T7	38		T9	7
valid_sources[0x23]	7381	1			T2	3		T3	49		T4	21
valid_sources[0x24]	7773	1			T2	2		T4	27		T6	8
valid_sources[0x25]	7177	1			T2	4		T4	21		T6	26
valid_sources[0x26]	15601	1			T2	10		T4	14		T7	24
valid_sources[0x27]	9004	1			T1	1		T2	3		T4	11
valid_sources[0x28]	7326	1			T2	6		T4	15		T6	16
valid_sources[0x29]	6939	1			T2	4		T4	15		T7	9
valid_sources[0x2a]	10993	1			T2	1		T4	22		T6	18
valid_sources[0x2b]	6691	1			T2	2		T4	25		T6	9
valid_sources[0x2c]	10226	1			T1	2		T2	5		T4	17
valid_sources[0x2d]	11334	1			T1	1		T2	3		T4	10
valid_sources[0x2e]	7020	1			T2	7		T4	15		T7	22
valid_sources[0x2f]	10198	1			T1	1		T2	2		T4	16
valid_sources[0x30]	7171	1			T2	10		T4	8		T6	1
valid_sources[0x31]	12695	1			T2	2		T4	25		T7	19
valid_sources[0x32]	7474	1			T2	1		T4	21		T6	3
valid_sources[0x33]	11807	1			T2	3		T4	20		T7	44
valid_sources[0x34]	6957	1			T2	5		T4	15		T7	31
valid_sources[0x35]	10961	1			T2	6		T4	29		T7	29
valid_sources[0x36]	9173	1			T4	8		T7	36		T9	13
valid_sources[0x37]	9299	1			T2	8		T4	13		T7	27
valid_sources[0x38]	6943	1			T2	2		T4	33		T6	1
valid_sources[0x39]	15698	1			T2	1		T4	17		T7	23
valid_sources[0x3a]	6966	1			T2	4		T4	10		T6	3
valid_sources[0x3b]	7726	1			T2	1		T4	19		T7	24
valid_sources[0x3c]	8628	1			T2	1		T4	24		T6	20
valid_sources[0x3d]	7523	1			T2	3		T4	28		T6	1
valid_sources[0x3e]	9625	1			T2	1		T4	13		T7	34
valid_sources[0x3f]	13042	1			T1	1		T2	4		T4	17
valid_sources[0x40]	16964	1			T1	1		T2	2		T4	19
valid_sources[0x41]	7331	1			T4	21		T6	11		T7	35
valid_sources[0x42]	10747	1			T1	1		T2	4		T4	18
valid_sources[0x43]	7325	1			T2	7		T4	6		T7	52
valid_sources[0x44]	11267	1			T1	1		T2	5		T4	37
valid_sources[0x45]	11196	1			T1	1		T2	4		T4	15
valid_sources[0x46]	20060	1			T2	1		T4	36		T6	11
valid_sources[0x47]	6864	1			T2	2		T4	23		T7	28
valid_sources[0x48]	11062	1			T1	2		T2	3		T4	15
valid_sources[0x49]	8414	1			T2	4		T4	12		T6	26
valid_sources[0x4a]	8449	1			T2	4		T4	8		T7	26
valid_sources[0x4b]	6805	1			T2	1		T4	10		T7	36
valid_sources[0x4c]	6961	1			T2	3		T4	6		T6	7
valid_sources[0x4d]	7420	1			T2	3		T4	26		T7	29
valid_sources[0x4e]	6742	1			T2	1		T4	15		T7	26
valid_sources[0x4f]	8821	1			T2	2		T4	15		T6	2
valid_sources[0x50]	6838	1			T1	2		T2	2		T4	16
valid_sources[0x51]	7250	1			T2	9		T4	34		T7	28
valid_sources[0x52]	8828	1			T2	4		T4	13		T6	12
valid_sources[0x53]	6781	1			T2	3		T4	30		T6	5
valid_sources[0x54]	7284	1			T1	1		T2	3		T4	25
valid_sources[0x55]	7507	1			T2	2		T4	10		T6	2
valid_sources[0x56]	12001	1			T2	2		T4	15		T6	21
valid_sources[0x57]	8224	1			T2	4		T4	15		T7	42
valid_sources[0x58]	10077	1			T7	22		T9	6		T36	1
valid_sources[0x59]	11567	1			T2	1		T4	7		T6	18
valid_sources[0x5a]	7225	1			T2	2		T4	26		T6	4
valid_sources[0x5b]	8001	1			T2	10		T4	14		T6	4
valid_sources[0x5c]	7105	1			T2	7		T4	17		T6	7
valid_sources[0x5d]	6982	1			T2	5		T4	30		T7	21
valid_sources[0x5e]	12406	1			T2	3		T4	6		T7	16
valid_sources[0x5f]	6992	1			T2	1		T4	6		T6	5
valid_sources[0x60]	7822	1			T1	2		T2	2		T4	14
valid_sources[0x61]	6913	1			T2	8		T4	9		T6	7
valid_sources[0x62]	7288	1			T2	1		T4	11		T6	8
valid_sources[0x63]	7019	1			T2	3		T4	19		T7	27
valid_sources[0x64]	6886	1			T2	6		T4	9		T6	4
valid_sources[0x65]	7193	1			T2	5		T4	18		T6	4
valid_sources[0x66]	10378	1			T2	7		T4	10		T7	29
valid_sources[0x67]	7937	1			T2	9		T4	7		T6	3
valid_sources[0x68]	8736	1			T2	2		T4	21		T7	27
valid_sources[0x69]	6943	1			T2	1		T4	19		T7	18
valid_sources[0x6a]	7205	1			T2	2		T4	19		T6	13
valid_sources[0x6b]	11164	1			T1	1		T2	1		T4	31
valid_sources[0x6c]	7066	1			T2	9		T4	12		T7	34
valid_sources[0x6d]	11729	1			T2	3		T4	33		T7	37
valid_sources[0x6e]	7255	1			T2	1		T4	27		T7	26
valid_sources[0x6f]	7322	1			T1	1		T2	6		T4	21
valid_sources[0x70]	10573	1			T2	3		T4	9		T6	3
valid_sources[0x71]	7105	1			T2	3		T4	33		T6	13
valid_sources[0x72]	11221	1			T2	1		T4	22		T7	33
valid_sources[0x73]	6831	1			T2	8		T4	10		T6	4
valid_sources[0x74]	7005	1			T2	8		T4	32		T6	2
valid_sources[0x75]	7114	1			T4	24		T7	38		T9	9
valid_sources[0x76]	11188	1			T2	7		T4	15		T6	7
valid_sources[0x77]	6662	1			T2	3		T4	15		T6	6
valid_sources[0x78]	9584	1			T2	1		T4	24		T6	9
valid_sources[0x79]	9937	1			T1	2		T2	4		T4	13
valid_sources[0x7a]	7385	1			T2	3		T4	10		T7	19
valid_sources[0x7b]	7249	1			T4	24		T6	1		T7	31
valid_sources[0x7c]	10061	1			T2	3		T4	12		T6	11
valid_sources[0x7d]	6903	1			T2	2		T4	10		T6	7
valid_sources[0x7e]	12440	1			T2	5		T4	20		T6	14
valid_sources[0x7f]	13039	1			T2	3		T4	21		T6	6
valid_sources[0x80]	10719	1			T1	1		T4	12		T7	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1046629

1

T2

440

T13

1

T4

2045

values[0x0]

all_enables

biggest_size

81625

1

T1

19

T2

39

T3

16

values[0x1]

all_enables

biggest_size

58977

1

T1

13

T2

16

T3

12