Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31669	1			T2	7		T4	6		T5	6
auto[PWRUP]	132	1			T14	1		T31	3		T148	3
auto[ONEST_0]	72	1			T11	1		T31	1		T38	1
auto[ONEST_021]	14	1			T200	1		T144	1		T20	1
auto[ONEST_1]	100	1			T10	1		T11	2		T148	1
auto[ONEST_DONE]	4	1			T31	1		T201	1		T202	1
auto[LP_0]	140	1			T7	2		T10	1		T36	1
auto[LP_021]	32	1			T7	1		T11	1		T148	1
auto[LP_1]	127	1			T7	3		T36	3		T11	1
auto[LP_EVAL]	73	1			T36	1		T11	2		T31	1
auto[LP_SLP]	550	1			T7	7		T36	5		T11	14
auto[LP_PWRUP]	28	1			T10	1		T11	1		T31	1
auto[NP_0]	142	1			T36	3		T11	1		T31	2
auto[NP_021]	34	1			T7	1		T36	1		T11	1
auto[NP_1]	174	1			T7	1		T11	3		T31	2
auto[NP_EVAL]	29	1			T7	1		T36	1		T37	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T148

1

T200

1

T47

2

min

31114

1

T2

7

T4

6

T5

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31117	1			T2	7		T4	6		T5	6
pow[0x1]	11	1			T203	1		T204	1		T205	1
pow[0x2]	14	1			T31	1		T148	1		T49	1
pow[0x3]	28	1			T11	1		T31	1		T206	1
pow[0x4]	53	1			T31	1		T16	2		T201	1
pow[0x5]	136	1			T7	2		T36	2		T11	1
pow[0x6]	276	1			T7	3		T36	3		T11	2
pow[0x7]	546	1			T7	2		T36	5		T11	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

221

1

T7

4

T10

2

T36

2

min

30582

1

T2

7

T4

6

T5

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30582	1			T2	7		T4	6		T5	6
pow[0x4]	1	1			T207	1		-	-		-	-
pow[0x5]	1	1			T208	1		-	-		-	-
pow[0x6]	3	1			T202	1		T191	1		T209	1
pow[0x7]	3	1			T210	1		T211	1		T209	1
pow[0x8]	1	1			T210	1		-	-		-	-
pow[0x9]	9	1			T200	1		T212	1		T47	1
pow[0xa]	26	1			T7	2		T16	2		T48	1
pow[0xb]	37	1			T7	1		T11	1		T148	1
pow[0xc]	56	1			T36	1		T11	1		T148	1
pow[0xd]	155	1			T11	4		T31	1		T16	1
pow[0xe]	352	1			T7	5		T10	1		T36	5
pow[0xf]	636	1			T7	4		T10	1		T36	7