Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2409	1			T6	4		T7	31		T10	15
auto[PWRUP]	141	1			T7	3		T10	1		T36	1
auto[ONEST_0]	75	1			T11	1		T31	1		T16	1
auto[ONEST_021]	16	1			T48	1		T49	1		T200	1
auto[ONEST_1]	99	1			T10	1		T11	1		T16	1
auto[ONEST_DONE]	3	1			T335	1		T336	2		-	-
auto[LP_0]	138	1			T11	4		T15	1		T16	2
auto[LP_021]	32	1			T7	1		T36	1		T31	1
auto[LP_1]	146	1			T7	1		T36	1		T15	1
auto[LP_EVAL]	66	1			T10	1		T14	1		T16	1
auto[LP_SLP]	597	1			T7	7		T10	4		T36	4
auto[LP_PWRUP]	34	1			T31	1		T148	1		T203	1
auto[NP_0]	259	1			T7	3		T10	2		T11	2
auto[NP_021]	57	1			T7	2		T36	1		T16	1
auto[NP_1]	226	1			T7	1		T10	1		T36	1
auto[NP_EVAL]	40	1			T10	2		T201	1		T200	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T208

1

T337

1

T235

1

min

2057

1

T6

4

T7

12

T10

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2073	1			T6	4		T7	12		T10	20
pow[0x1]	12	1			T15	1		T37	1		T43	1
pow[0x2]	15	1			T48	2		T208	1		T43	1
pow[0x3]	25	1			T148	1		T48	1		T208	1
pow[0x4]	85	1			T7	1		T36	1		T31	1
pow[0x5]	144	1			T7	2		T36	1		T11	1
pow[0x6]	288	1			T7	7		T10	2		T36	2
pow[0x7]	568	1			T7	6		T10	2		T36	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

226

1

T7

7

T36

3

T11

3

min

1404

1

T6

4

T7

8

T10

14

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1411	1			T6	4		T7	8		T10	14
pow[0x1]	22	1			T15	3		T38	1		T43	1
pow[0x2]	33	1			T10	4		T14	2		T40	1
pow[0x3]	63	1			T14	2		T38	2		T39	2
pow[0x4]	43	1			T15	1		T16	3		T37	1
pow[0x6]	1	1			T264	1		-	-		-	-
pow[0x7]	2	1			T7	1		T148	1		-	-
pow[0x8]	3	1			T338	1		T339	1		T340	1
pow[0x9]	12	1			T48	1		T337	1		T144	1
pow[0xa]	20	1			T16	1		T148	1		T48	1
pow[0xb]	39	1			T11	2		T48	2		T201	1
pow[0xc]	72	1			T11	2		T31	1		T148	1
pow[0xd]	159	1			T7	6		T36	1		T11	4
pow[0xe]	318	1			T7	3		T10	1		T36	4
pow[0xf]	654	1			T7	5		T10	5		T36	4