Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T10

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T6,T9,T10
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Covered	T6,T9,T11
1	0	Covered	T6,T9,T10

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T6,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T7,T12,T24
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T24
0	1	Covered	T7,T12,T24
1	0	Covered	T7,T12,T24

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T6,T9,T10
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Covered	T6,T9,T11
1	0	Covered	T6,T9,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T6,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T7,T12,T24
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T24
0	1	Covered	T7,T12,T24
1	0	Covered	T7,T12,T24

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T8,T9
1	1	0	Covered	T5,T6,T8
1	1	1	Covered	T5,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T8,T9
1	1	0	Covered	T5,T6,T8
1	1	1	Covered	T5,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T8,T9
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T5,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T8
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T5,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T6,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T6,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T4,T5
1	1	Covered	T5,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T24
1	0	Covered	T7,T8,T24

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T24
1	0	Covered	T7,T8,T24

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T24
1	0	Covered	T8,T24,T29
1	1	Covered	T7,T8,T24

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T9,T10

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T9,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T12,T24

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T12,T24

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34956166	34621621	0	0
gen_filter_match[0].MatchCheck00_A	34956166	10971311	0	0
gen_filter_match[0].MatchCheck01_A	34956166	3055294	0	0
gen_filter_match[0].MatchCheck10_A	34956166	2351185	0	0
gen_filter_match[0].MatchCheck11_A	34956166	18243831	0	0
gen_filter_match[1].MatchCheck00_A	34956166	11262388	0	0
gen_filter_match[1].MatchCheck01_A	34956166	1271004	0	0
gen_filter_match[1].MatchCheck10_A	34956166	1176237	0	0
gen_filter_match[1].MatchCheck11_A	34956166	20911992	0	0
gen_filter_match[2].MatchCheck00_A	34956166	12536954	0	0
gen_filter_match[2].MatchCheck01_A	34956166	962948	0	0
gen_filter_match[2].MatchCheck10_A	34956166	610799	0	0
gen_filter_match[2].MatchCheck11_A	34956166	20510920	0	0
gen_filter_match[3].MatchCheck00_A	34956166	11754376	0	0
gen_filter_match[3].MatchCheck01_A	34956166	453847	0	0
gen_filter_match[3].MatchCheck10_A	34956166	341637	0	0
gen_filter_match[3].MatchCheck11_A	34956166	22071761	0	0
gen_filter_match[4].MatchCheck00_A	34956166	13007102	0	0
gen_filter_match[4].MatchCheck01_A	34956166	81055	0	0
gen_filter_match[4].MatchCheck10_A	34956166	65	0	0
gen_filter_match[4].MatchCheck11_A	34956166	21533399	0	0
gen_filter_match[5].MatchCheck00_A	34956166	13610371	0	0
gen_filter_match[5].MatchCheck01_A	34956166	31924	0	0
gen_filter_match[5].MatchCheck10_A	34956166	94	0	0
gen_filter_match[5].MatchCheck11_A	34956166	20979232	0	0
gen_filter_match[6].MatchCheck00_A	34956166	12937142	0	0
gen_filter_match[6].MatchCheck01_A	34956166	118167	0	0
gen_filter_match[6].MatchCheck10_A	34956166	32291	0	0
gen_filter_match[6].MatchCheck11_A	34956166	21534021	0	0
gen_filter_match[7].MatchCheck00_A	34956166	12943861	0	0
gen_filter_match[7].MatchCheck01_A	34956166	272075	0	0
gen_filter_match[7].MatchCheck10_A	34956166	89883	0	0
gen_filter_match[7].MatchCheck11_A	34956166	21315802	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	34621621	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	33939	0	0
T5	32907	32853	0	0
T6	107826	107450	0	0
T7	111023	107182	0	0
T8	78082	78000	0	0
T9	98553	98468	0	0
T13	109	15	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	10971311	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	4	0	0
T5	32907	4	0	0
T6	107826	75599	0	0
T7	111023	106838	0	0
T8	78082	4	0	0
T9	98553	66525	0	0
T13	109	15	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	3055294	0	0
T10	19964	7000	0	0
T11	59434	0	0	0
T12	66316	0	0	0
T14	22656	15278	0	0
T24	108919	0	0	0
T25	1146	0	0	0
T35	32519	0	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T48	0	33149	0	0
T54	0	32866	0	0
T127	0	66330	0	0
T128	0	35936	0	0
T129	0	32318	0	0
T130	0	37589	0	0
T131	0	33894	0	0
T132	0	87340	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	2351185	0	0
T15	18232	12402	0	0
T16	0	13939	0	0
T24	108919	37176	0	0
T25	1146	0	0	0
T26	65700	0	0	0
T27	98181	0	0	0
T28	39843	0	0	0
T29	79296	0	0	0
T30	4361	0	0	0
T31	19109	0	0	0
T37	0	8939	0	0
T39	0	5955	0	0
T129	0	33101	0	0
T133	0	36744	0	0
T134	0	1	0	0
T135	0	33193	0	0
T136	0	36082	0	0
T137	903	0	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	18243831	0	0
T4	34022	33935	0	0
T5	32907	32849	0	0
T6	107826	31851	0	0
T7	111023	344	0	0
T8	78082	77996	0	0
T9	98553	31943	0	0
T10	19964	326	0	0
T11	0	843	0	0
T12	0	32610	0	0
T36	14980	262	0	0
T41	730	0	0	0
T42	1165	0	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	11262388	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	33939	0	0
T5	32907	4	0	0
T6	107826	73841	0	0
T7	111023	107182	0	0
T8	78082	4	0	0
T9	98553	4	0	0
T13	109	15	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	1271004	0	0
T6	107826	33609	0	0
T7	111023	0	0	0
T8	78082	0	0	0
T9	98553	33456	0	0
T10	19964	0	0	0
T11	59434	0	0	0
T12	66316	0	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T134	0	1	0	0
T138	0	33872	0	0
T139	0	32667	0	0
T140	0	1	0	0
T141	0	34500	0	0
T142	0	33893	0	0
T143	0	33508	0	0
T144	0	33138	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	1176237	0	0
T16	78025	1	0	0
T17	0	28	0	0
T37	34978	12762	0	0
T43	0	2259	0	0
T45	122736	0	0	0
T46	118101	0	0	0
T54	99625	0	0	0
T126	0	34039	0	0
T128	102753	0	0	0
T134	0	1	0	0
T138	33954	0	0	0
T140	0	1	0	0
T145	0	31652	0	0
T146	0	1	0	0
T147	0	33777	0	0
T148	23374	0	0	0
T149	68442	0	0	0
T150	5207	0	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	20911992	0	0
T5	32907	32849	0	0
T6	107826	0	0	0
T7	111023	0	0	0
T8	78082	77996	0	0
T9	98553	65008	0	0
T10	19964	7000	0	0
T11	59434	0	0	0
T12	0	33643	0	0
T24	0	37176	0	0
T26	0	65616	0	0
T27	0	98105	0	0
T28	0	39741	0	0
T35	0	32418	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	12536954	0	0
T1	1108	1013	0	0
T2	34277	3	0	0
T3	7247	7187	0	0
T4	34022	33939	0	0
T5	32907	4	0	0
T6	107826	8512	0	0
T7	111023	28199	0	0
T8	78082	4	0	0
T9	98553	33460	0	0
T13	109	15	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	962948	0	0
T20	0	2700	0	0
T67	68	0	0	0
T129	65522	0	0	0
T134	0	1	0	0
T140	0	1	0	0
T145	31752	0	0	0
T151	97443	1	0	0
T152	0	85163	0	0
T153	0	32781	0	0
T154	0	33827	0	0
T155	0	39944	0	0
T156	0	33849	0	0
T157	0	32693	0	0
T158	6239	0	0	0
T159	66012	0	0	0
T160	97946	0	0	0
T161	625	0	0	0
T162	1181	0	0	0
T163	1045	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	610799	0	0
T7	111023	32906	0	0
T8	78082	0	0	0
T9	98553	0	0	0
T10	19964	0	0	0
T11	59434	0	0	0
T12	66316	0	0	0
T16	0	1	0	0
T35	32519	0	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T127	0	32228	0	0
T130	0	37892	0	0
T132	0	35090	0	0
T134	0	1	0	0
T140	0	1	0	0
T146	0	1	0	0
T164	0	1	0	0
T165	0	31561	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	20510920	0	0
T2	34277	34188	0	0
T3	7247	0	0	0
T4	34022	0	0	0
T5	32907	32849	0	0
T6	107826	98938	0	0
T7	111023	46077	0	0
T8	78082	77996	0	0
T9	98553	65008	0	0
T10	19964	7000	0	0
T12	0	33643	0	0
T13	109	0	0	0
T14	0	15277	0	0
T35	0	32418	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	11754376	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	33939	0	0
T5	32907	4	0	0
T6	107826	73841	0	0
T7	111023	107182	0	0
T8	78082	4	0	0
T9	98553	4	0	0
T13	109	15	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	453847	0	0
T67	68	0	0	0
T78	0	32786	0	0
T128	102753	33175	0	0
T134	0	1	0	0
T140	0	1	0	0
T150	5207	0	0	0
T151	97443	0	0	0
T157	0	33672	0	0
T158	6239	0	0	0
T159	66012	0	0	0
T160	97946	0	0	0
T161	625	0	0	0
T162	1181	0	0	0
T166	0	37912	0	0
T167	0	12473	0	0
T168	0	2	0	0
T169	0	6787	0	0
T170	0	1	0	0
T171	574	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	341637	0	0
T11	59434	1	0	0
T12	66316	0	0	0
T14	22656	0	0	0
T16	0	3	0	0
T17	0	27	0	0
T24	108919	0	0	0
T25	1146	0	0	0
T26	65700	0	0	0
T27	98181	0	0	0
T28	39843	0	0	0
T29	79296	0	0	0
T35	32519	0	0	0
T134	0	2	0	0
T140	0	1	0	0
T146	0	1	0	0
T151	0	1	0	0
T164	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	22071761	0	0
T5	32907	32849	0	0
T6	107826	33609	0	0
T7	111023	0	0	0
T8	78082	77996	0	0
T9	98553	98464	0	0
T10	19964	7000	0	0
T11	59434	32822	0	0
T12	0	66253	0	0
T14	0	15277	0	0
T24	0	108830	0	0
T35	0	32418	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	13007102	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	33939	0	0
T5	32907	4	0	0
T6	107826	73841	0	0
T7	111023	61105	0	0
T8	78082	4	0	0
T9	98553	33460	0	0
T13	109	15	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	81055	0	0
T7	111023	46077	0	0
T8	78082	0	0	0
T9	98553	0	0	0
T10	19964	0	0	0
T11	59434	0	0	0
T12	66316	0	0	0
T35	32519	0	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T140	0	1	0	0
T151	0	1	0	0
T157	0	1	0	0
T168	0	3	0	0
T170	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	34968	0	0
T177	0	1	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	65	0	0
T8	78082	1	0	0
T9	98553	0	0	0
T10	19964	0	0	0
T11	59434	1	0	0
T12	66316	0	0	0
T14	22656	0	0	0
T16	0	1	0	0
T35	32519	1	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T151	0	1	0	0
T164	0	1	0	0
T173	0	1	0	0
T178	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	21533399	0	0
T5	32907	32849	0	0
T6	107826	33609	0	0
T7	111023	0	0	0
T8	78082	77995	0	0
T9	98553	65008	0	0
T10	19964	7000	0	0
T11	59434	32822	0	0
T12	0	33643	0	0
T14	0	15277	0	0
T24	0	36102	0	0
T35	0	32417	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	13610371	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	33939	0	0
T5	32907	4	0	0
T6	107826	107450	0	0
T7	111023	28199	0	0
T8	78082	4	0	0
T9	98553	33069	0	0
T13	109	15	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	31924	0	0
T132	122494	1	0	0
T133	36804	0	0	0
T139	96814	0	0	0
T140	0	1	0	0
T157	0	1	0	0
T168	0	2	0	0
T174	0	1	0	0
T176	0	1	0	0
T178	33034	0	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	97749	0	0	0
T184	545	0	0	0
T185	33288	0	0	0
T186	98650	0	0	0
T187	62	0	0	0
T188	100486	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	94	0	0
T8	78082	1	0	0
T9	98553	0	0	0
T10	19964	0	0	0
T11	59434	0	0	0
T12	66316	0	0	0
T14	22656	0	0	0
T16	0	4	0	0
T35	32519	1	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T135	0	1	0	0
T140	0	1	0	0
T164	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T178	0	1	0	0
T189	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	20979232	0	0
T5	32907	32849	0	0
T6	107826	0	0	0
T7	111023	78983	0	0
T8	78082	77995	0	0
T9	98553	65399	0	0
T10	19964	7000	0	0
T11	59434	0	0	0
T24	0	73278	0	0
T26	0	65616	0	0
T27	0	98105	0	0
T29	0	79232	0	0
T35	0	32417	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	12937142	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	4	0	0
T5	32907	4	0	0
T6	107826	41990	0	0
T7	111023	107182	0	0
T8	78082	4	0	0
T9	98553	65403	0	0
T13	109	15	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	118167	0	0
T67	68	0	0	0
T129	65522	0	0	0
T132	0	1	0	0
T145	31752	0	0	0
T147	0	32253	0	0
T151	97443	1	0	0
T158	6239	0	0	0
T159	66012	0	0	0
T160	97946	0	0	0
T161	625	0	0	0
T162	1181	0	0	0
T163	1045	0	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T190	0	32179	0	0
T191	0	833	0	0
T192	0	1	0	0
T193	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	32291	0	0
T8	78082	1	0	0
T9	98553	0	0	0
T10	19964	0	0	0
T11	59434	0	0	0
T12	66316	0	0	0
T14	22656	0	0	0
T16	0	1	0	0
T35	32519	1	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T135	0	1	0	0
T140	0	1	0	0
T164	0	1	0	0
T172	0	1	0	0
T185	0	1	0	0
T189	0	1	0	0
T194	0	32195	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	21534021	0	0
T4	34022	33935	0	0
T5	32907	32849	0	0
T6	107826	65460	0	0
T7	111023	0	0	0
T8	78082	77995	0	0
T9	98553	33065	0	0
T10	19964	0	0	0
T12	0	33643	0	0
T24	0	73278	0	0
T26	0	65616	0	0
T27	0	98105	0	0
T35	0	32417	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	12943861	0	0
T1	1108	1013	0	0
T2	34277	34191	0	0
T3	7247	7187	0	0
T4	34022	4	0	0
T5	32907	4	0	0
T6	107826	75599	0	0
T7	111023	107182	0	0
T8	78082	4	0	0
T9	98553	65403	0	0
T13	109	15	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	272075	0	0
T67	68	0	0	0
T82	0	1	0	0
T129	65522	0	0	0
T132	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T140	0	1	0	0
T145	31752	0	0	0
T151	97443	1	0	0
T158	6239	0	0	0
T159	66012	0	0	0
T160	97946	0	0	0
T161	625	0	0	0
T162	1181	0	0	0
T163	1045	0	0	0
T195	0	32662	0	0
T196	0	33376	0	0
T197	0	1	0	0
T198	0	31990	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	89883	0	0
T4	34022	1	0	0
T5	32907	0	0	0
T6	107826	0	0	0
T7	111023	0	0	0
T8	78082	1	0	0
T9	98553	0	0	0
T10	19964	0	0	0
T11	0	1	0	0
T16	0	1	0	0
T35	0	1	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0
T45	0	1	0	0
T134	0	1	0	0
T151	0	1	0	0
T185	0	1	0	0
T199	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34956166	21315802	0	0
T4	34022	33934	0	0
T5	32907	32849	0	0
T6	107826	31851	0	0
T7	111023	0	0	0
T8	78082	77995	0	0
T9	98553	33065	0	0
T10	19964	7000	0	0
T11	0	32821	0	0
T12	0	33643	0	0
T24	0	108830	0	0
T35	0	32417	0	0
T36	14980	0	0	0
T41	730	0	0	0
T42	1165	0	0	0