Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2145	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2100	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2041	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2215	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2310	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2239	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2018	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2319	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2271	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2225	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2033	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1877	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2144	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2129	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2125	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2168	0	0
adc_en_ctl_rd_A	2147483647	1952	0	0
adc_fsm_rst_rd_A	2147483647	1589	0	0
adc_intr_ctl_rd_A	2147483647	1812	0	0
adc_lp_sample_ctl_rd_A	2147483647	1693	0	0
adc_pd_ctl_rd_A	2147483647	1813	0	0
adc_sample_ctl_rd_A	2147483647	1637	0	0
adc_wakeup_ctl_rd_A	2147483647	1837	0	0
intr_enable_rd_A	2147483647	2244	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2145	0	0
T14	543773	24	0	0
T15	419373	13	0	0
T16	0	16	0	0
T17	0	30	0	0
T18	0	45	0	0
T19	0	48	0	0
T20	0	24	0	0
T21	0	18	0	0
T22	0	36	0	0
T23	0	39	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2100	0	0
T14	543773	16	0	0
T15	419373	27	0	0
T16	0	14	0	0
T17	0	41	0	0
T18	0	45	0	0
T19	0	33	0	0
T20	0	8	0	0
T21	0	9	0	0
T22	0	29	0	0
T23	0	33	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2041	0	0
T14	543773	19	0	0
T15	419373	14	0	0
T16	0	21	0	0
T17	0	34	0	0
T18	0	32	0	0
T19	0	35	0	0
T20	0	17	0	0
T22	0	39	0	0
T23	0	52	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0
T32	0	16	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2215	0	0
T14	543773	25	0	0
T15	419373	39	0	0
T16	0	17	0	0
T17	0	35	0	0
T18	0	31	0	0
T19	0	39	0	0
T20	0	35	0	0
T21	0	8	0	0
T22	0	34	0	0
T23	0	45	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2310	0	0
T14	543773	28	0	0
T15	419373	7	0	0
T16	0	15	0	0
T17	0	44	0	0
T18	0	27	0	0
T19	0	37	0	0
T20	0	15	0	0
T21	0	7	0	0
T22	0	39	0	0
T23	0	52	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2239	0	0
T14	543773	15	0	0
T15	419373	44	0	0
T16	0	16	0	0
T17	0	27	0	0
T18	0	32	0	0
T19	0	30	0	0
T20	0	27	0	0
T21	0	9	0	0
T22	0	31	0	0
T23	0	52	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2018	0	0
T14	543773	18	0	0
T15	419373	15	0	0
T16	0	12	0	0
T17	0	39	0	0
T18	0	43	0	0
T19	0	30	0	0
T20	0	24	0	0
T21	0	16	0	0
T22	0	34	0	0
T23	0	46	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2319	0	0
T14	543773	17	0	0
T15	419373	29	0	0
T16	0	19	0	0
T17	0	24	0	0
T18	0	27	0	0
T19	0	35	0	0
T20	0	24	0	0
T21	0	4	0	0
T22	0	27	0	0
T23	0	40	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2271	0	0
T14	543773	37	0	0
T15	419373	19	0	0
T16	0	14	0	0
T17	0	44	0	0
T18	0	27	0	0
T19	0	45	0	0
T20	0	19	0	0
T21	0	6	0	0
T22	0	36	0	0
T23	0	38	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T14	543773	19	0	0
T15	419373	9	0	0
T16	0	23	0	0
T17	0	29	0	0
T18	0	38	0	0
T19	0	41	0	0
T20	0	19	0	0
T21	0	12	0	0
T22	0	66	0	0
T23	0	34	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T14	543773	4	0	0
T15	419373	13	0	0
T16	0	19	0	0
T17	0	30	0	0
T18	0	20	0	0
T19	0	49	0	0
T20	0	11	0	0
T21	0	7	0	0
T22	0	46	0	0
T23	0	36	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1877	0	0
T14	543773	17	0	0
T15	419373	26	0	0
T16	0	13	0	0
T17	0	38	0	0
T18	0	30	0	0
T19	0	33	0	0
T20	0	12	0	0
T21	0	5	0	0
T22	0	54	0	0
T23	0	36	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2144	0	0
T14	543773	16	0	0
T15	419373	16	0	0
T16	0	19	0	0
T17	0	28	0	0
T18	0	12	0	0
T19	0	40	0	0
T20	0	17	0	0
T21	0	10	0	0
T22	0	34	0	0
T23	0	25	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2129	0	0
T14	543773	17	0	0
T15	419373	30	0	0
T16	0	7	0	0
T17	0	37	0	0
T18	0	32	0	0
T19	0	35	0	0
T20	0	16	0	0
T21	0	6	0	0
T22	0	31	0	0
T23	0	35	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2125	0	0
T14	543773	31	0	0
T15	419373	17	0	0
T16	0	11	0	0
T17	0	25	0	0
T18	0	33	0	0
T19	0	54	0	0
T20	0	32	0	0
T21	0	12	0	0
T22	0	39	0	0
T23	0	26	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2168	0	0
T14	543773	28	0	0
T15	419373	14	0	0
T16	0	25	0	0
T17	0	21	0	0
T18	0	36	0	0
T19	0	36	0	0
T20	0	6	0	0
T21	0	18	0	0
T22	0	32	0	0
T23	0	19	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1952	0	0
T14	543773	20	0	0
T15	419373	35	0	0
T16	0	26	0	0
T17	0	27	0	0
T18	0	49	0	0
T19	0	39	0	0
T20	0	21	0	0
T21	0	17	0	0
T22	0	24	0	0
T23	0	39	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1589	0	0
T14	543773	28	0	0
T15	419373	11	0	0
T16	0	13	0	0
T17	0	29	0	0
T18	0	16	0	0
T19	0	49	0	0
T20	0	14	0	0
T22	0	33	0	0
T23	0	27	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0
T32	0	20	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1812	0	0
T14	543773	31	0	0
T15	419373	33	0	0
T16	0	18	0	0
T17	0	13	0	0
T18	0	25	0	0
T19	0	41	0	0
T20	0	41	0	0
T21	0	3	0	0
T22	0	19	0	0
T23	0	51	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1693	0	0
T14	543773	4	0	0
T15	419373	28	0	0
T16	0	10	0	0
T17	0	38	0	0
T18	0	49	0	0
T19	0	46	0	0
T20	0	20	0	0
T22	0	41	0	0
T23	0	41	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0
T32	0	18	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1813	0	0
T14	543773	47	0	0
T15	419373	26	0	0
T16	0	14	0	0
T17	0	37	0	0
T18	0	34	0	0
T19	0	34	0	0
T20	0	14	0	0
T21	0	5	0	0
T22	0	30	0	0
T23	0	35	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1637	0	0
T14	543773	24	0	0
T15	419373	20	0	0
T16	0	18	0	0
T17	0	31	0	0
T18	0	47	0	0
T19	0	48	0	0
T20	0	19	0	0
T21	0	7	0	0
T22	0	34	0	0
T23	0	36	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T14	543773	20	0	0
T15	419373	19	0	0
T16	0	22	0	0
T17	0	46	0	0
T18	0	30	0	0
T19	0	50	0	0
T20	0	39	0	0
T21	0	6	0	0
T22	0	48	0	0
T23	0	35	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T30	523421	0	0	0
T31	945998	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2244	0	0
T11	475480	18	0	0
T12	258626	0	0	0
T14	543773	41	0	0
T15	0	67	0	0
T16	0	51	0	0
T17	0	48	0	0
T18	0	51	0	0
T19	0	51	0	0
T20	0	25	0	0
T24	522801	0	0	0
T25	74556	0	0	0
T26	788413	0	0	0
T27	486002	0	0	0
T28	896693	0	0	0
T29	360807	0	0	0
T33	0	26	0	0
T34	0	13	0	0
T35	406504	0	0	0