Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1207746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1181640

1

T4

5

T1

2088

T2

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2094490	1			T4	1		T1	4070		T3	841
values[0x0]	146331	1			T4	9		T1	124		T2	29
values[0x1]	148565	1			T4	12		T1	118		T2	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	967165	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1422221

1

T4

7

T1

2522

T2

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8205	1			T1	17		T5	2		T6	7
valid_sources[0x01]	9523	1			T1	16		T5	2		T8	6
valid_sources[0x02]	11417	1			T1	8		T2	1		T5	4
valid_sources[0x03]	7277	1			T1	13		T2	1		T6	10
valid_sources[0x04]	11549	1			T1	15		T2	1		T5	5
valid_sources[0x05]	9915	1			T1	23		T6	9		T8	10
valid_sources[0x06]	11048	1			T1	17		T5	3		T7	1
valid_sources[0x07]	7089	1			T1	15		T2	1		T5	3
valid_sources[0x08]	7219	1			T1	18		T5	3		T6	7
valid_sources[0x09]	9232	1			T1	16		T5	7		T8	16
valid_sources[0x0a]	6852	1			T1	21		T2	1		T5	4
valid_sources[0x0b]	7755	1			T1	21		T2	1		T6	18
valid_sources[0x0c]	7740	1			T1	18		T5	2		T8	2
valid_sources[0x0d]	7246	1			T1	17		T5	6		T6	7
valid_sources[0x0e]	8846	1			T1	17		T5	5		T8	24
valid_sources[0x0f]	7099	1			T1	15		T5	2		T6	9
valid_sources[0x10]	7185	1			T1	16		T5	4		T8	7
valid_sources[0x11]	7243	1			T1	12		T5	4		T6	5
valid_sources[0x12]	8024	1			T1	13		T5	5		T6	2
valid_sources[0x13]	7275	1			T1	13		T2	1		T5	6
valid_sources[0x14]	7645	1			T1	19		T5	3		T6	34
valid_sources[0x15]	8320	1			T1	8		T5	4		T6	8
valid_sources[0x16]	9167	1			T1	15		T2	1		T5	2
valid_sources[0x17]	7343	1			T1	20		T5	3		T8	13
valid_sources[0x18]	7073	1			T1	14		T5	1		T6	15
valid_sources[0x19]	8209	1			T4	1		T1	14		T5	3
valid_sources[0x1a]	6934	1			T1	15		T5	10		T8	9
valid_sources[0x1b]	6787	1			T1	13		T5	8		T8	9
valid_sources[0x1c]	8076	1			T4	2		T1	19		T2	1
valid_sources[0x1d]	6996	1			T1	21		T2	1		T5	8
valid_sources[0x1e]	19912	1			T1	14		T5	1		T7	2
valid_sources[0x1f]	15091	1			T1	21		T5	1		T8	11
valid_sources[0x20]	10883	1			T1	15		T5	5		T6	20
valid_sources[0x21]	7899	1			T1	12		T5	5		T8	11
valid_sources[0x22]	7090	1			T1	13		T2	1		T5	2
valid_sources[0x23]	11147	1			T1	16		T5	2		T6	3
valid_sources[0x24]	10321	1			T1	20		T5	5		T8	13
valid_sources[0x25]	10453	1			T1	19		T8	7		T10	15
valid_sources[0x26]	6791	1			T1	24		T5	2		T6	10
valid_sources[0x27]	8154	1			T1	20		T2	1		T8	12
valid_sources[0x28]	12622	1			T1	16		T5	11		T8	10
valid_sources[0x29]	8819	1			T1	22		T5	3		T8	7
valid_sources[0x2a]	8109	1			T1	14		T5	5		T7	1
valid_sources[0x2b]	7011	1			T1	18		T6	7		T8	15
valid_sources[0x2c]	7201	1			T1	18		T2	1		T5	11
valid_sources[0x2d]	7227	1			T1	25		T6	2		T7	1
valid_sources[0x2e]	7125	1			T1	11		T6	10		T8	14
valid_sources[0x2f]	7081	1			T1	16		T5	7		T8	11
valid_sources[0x30]	7144	1			T1	19		T5	6		T6	3
valid_sources[0x31]	8254	1			T1	17		T5	7		T7	1
valid_sources[0x32]	7268	1			T1	25		T5	6		T6	1
valid_sources[0x33]	6657	1			T1	22		T5	10		T6	2
valid_sources[0x34]	6851	1			T1	21		T5	10		T8	12
valid_sources[0x35]	7285	1			T1	12		T5	5		T6	2
valid_sources[0x36]	7439	1			T1	18		T2	1		T5	3
valid_sources[0x37]	7288	1			T1	18		T5	2		T8	24
valid_sources[0x38]	7973	1			T1	8		T5	5		T7	2
valid_sources[0x39]	6719	1			T1	19		T5	4		T7	1
valid_sources[0x3a]	6975	1			T1	10		T8	8		T10	12
valid_sources[0x3b]	6805	1			T1	25		T5	5		T6	7
valid_sources[0x3c]	6866	1			T1	15		T5	3		T6	2
valid_sources[0x3d]	11833	1			T1	14		T5	4		T6	1
valid_sources[0x3e]	7840	1			T1	19		T5	1		T8	13
valid_sources[0x3f]	6795	1			T1	20		T5	6		T6	51
valid_sources[0x40]	7201	1			T4	4		T1	12		T5	3
valid_sources[0x41]	11451	1			T1	20		T5	12		T6	8
valid_sources[0x42]	10637	1			T1	17		T2	1		T5	1
valid_sources[0x43]	9219	1			T1	22		T2	1		T5	3
valid_sources[0x44]	7146	1			T1	16		T5	5		T6	2
valid_sources[0x45]	7371	1			T1	16		T5	4		T6	1
valid_sources[0x46]	6851	1			T1	16		T2	1		T5	9
valid_sources[0x47]	12689	1			T1	14		T2	1		T5	2
valid_sources[0x48]	6952	1			T1	19		T5	1		T6	1
valid_sources[0x49]	12143	1			T1	11		T5	4		T6	8
valid_sources[0x4a]	7045	1			T1	19		T5	2		T8	4
valid_sources[0x4b]	14381	1			T1	17		T5	2		T8	9
valid_sources[0x4c]	8729	1			T1	20		T5	2		T7	2
valid_sources[0x4d]	9153	1			T1	21		T5	2		T7	1
valid_sources[0x4e]	7495	1			T1	12		T8	15		T10	30
valid_sources[0x4f]	11708	1			T1	23		T8	12		T10	6
valid_sources[0x50]	16056	1			T1	15		T2	1		T5	5
valid_sources[0x51]	7093	1			T1	12		T5	3		T6	1
valid_sources[0x52]	10027	1			T1	21		T5	3		T6	13
valid_sources[0x53]	7057	1			T1	17		T7	2		T8	16
valid_sources[0x54]	8140	1			T1	18		T8	12		T10	15
valid_sources[0x55]	10459	1			T1	18		T5	5		T7	2
valid_sources[0x56]	10660	1			T1	15		T5	2		T6	3
valid_sources[0x57]	15708	1			T1	17		T7	3		T8	12
valid_sources[0x58]	6821	1			T1	13		T5	2		T7	1
valid_sources[0x59]	7124	1			T1	21		T2	1		T5	11
valid_sources[0x5a]	6995	1			T1	21		T5	7		T8	6
valid_sources[0x5b]	19741	1			T1	13		T5	7		T8	9
valid_sources[0x5c]	7398	1			T1	10		T6	5		T7	1
valid_sources[0x5d]	7718	1			T1	16		T5	3		T7	1
valid_sources[0x5e]	7212	1			T1	15		T5	3		T8	4
valid_sources[0x5f]	6696	1			T1	17		T5	6		T7	9
valid_sources[0x60]	7017	1			T1	26		T5	4		T8	9
valid_sources[0x61]	13846	1			T4	3		T1	14		T5	1
valid_sources[0x62]	7066	1			T1	21		T2	1		T5	1
valid_sources[0x63]	20569	1			T1	23		T5	7		T6	33
valid_sources[0x64]	11084	1			T1	16		T5	8		T8	11
valid_sources[0x65]	12157	1			T1	9		T5	3		T8	11
valid_sources[0x66]	7080	1			T1	22		T5	3		T7	2
valid_sources[0x67]	7331	1			T1	15		T7	1		T8	12
valid_sources[0x68]	7824	1			T1	25		T5	3		T6	3
valid_sources[0x69]	7138	1			T1	19		T5	6		T8	15
valid_sources[0x6a]	11475	1			T1	21		T5	3		T8	12
valid_sources[0x6b]	7159	1			T1	19		T5	7		T6	7
valid_sources[0x6c]	9835	1			T1	24		T2	2		T7	2
valid_sources[0x6d]	6966	1			T4	1		T1	9		T2	1
valid_sources[0x6e]	7344	1			T1	21		T5	3		T6	5
valid_sources[0x6f]	13576	1			T1	17		T2	2		T5	6
valid_sources[0x70]	7099	1			T1	14		T2	1		T5	4
valid_sources[0x71]	11347	1			T1	19		T5	5		T6	1
valid_sources[0x72]	7142	1			T1	21		T5	8		T8	15
valid_sources[0x73]	8016	1			T1	10		T5	3		T8	11
valid_sources[0x74]	14984	1			T1	15		T5	3		T6	3
valid_sources[0x75]	8203	1			T1	21		T5	6		T6	9
valid_sources[0x76]	12462	1			T1	17		T5	5		T8	11
valid_sources[0x77]	12877	1			T1	21		T5	4		T8	14
valid_sources[0x78]	8095	1			T4	1		T1	25		T8	6
valid_sources[0x79]	11398	1			T1	14		T5	4		T8	7
valid_sources[0x7a]	7343	1			T1	17		T2	1		T5	1
valid_sources[0x7b]	7107	1			T1	12		T5	12		T8	11
valid_sources[0x7c]	7972	1			T1	14		T5	7		T8	17
valid_sources[0x7d]	8144	1			T1	18		T5	3		T6	2
valid_sources[0x7e]	7409	1			T1	16		T2	2		T5	7
valid_sources[0x7f]	8324	1			T1	9		T5	2		T6	8
valid_sources[0x80]	8075	1			T1	15		T5	1		T8	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1043860

1

T1

1989

T3

425

T5

421

values[0x0]

all_enables

biggest_size

80027

1

T4

4

T1

63

T2

15

values[0x1]

all_enables

biggest_size

57753

1

T4

1

T1

36

T2

19