Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30449	1			T1	6		T3	7		T5	8
auto[PWRUP]	111	1			T40	2		T61	1		T50	2
auto[ONEST_0]	66	1			T6	4		T42	1		T50	1
auto[ONEST_021]	11	1			T91	1		T200	1		T201	1
auto[ONEST_1]	82	1			T6	1		T40	2		T42	1
auto[ONEST_DONE]	5	1			T40	1		T91	1		T202	1
auto[LP_0]	123	1			T40	3		T42	1		T203	1
auto[LP_021]	30	1			T6	1		T58	1		T204	1
auto[LP_1]	137	1			T6	1		T40	2		T42	1
auto[LP_EVAL]	61	1			T42	1		T50	2		T203	1
auto[LP_SLP]	554	1			T6	9		T40	4		T42	7
auto[LP_PWRUP]	29	1			T6	2		T40	2		T42	1
auto[NP_0]	139	1			T40	2		T42	1		T205	1
auto[NP_021]	31	1			T61	1		T58	1		T206	2
auto[NP_1]	179	1			T6	4		T40	3		T42	2
auto[NP_EVAL]	34	1			T61	1		T58	1		T205	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T42

1

T58

1

T59

1

min

29959

1

T1

6

T3

7

T5

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29965	1			T1	6		T3	7		T5	8
pow[0x1]	10	1			T203	1		T130	1		T207	2
pow[0x2]	17	1			T40	1		T59	1		T204	1
pow[0x3]	30	1			T50	1		T203	1		T206	3
pow[0x4]	71	1			T6	3		T40	2		T61	3
pow[0x5]	126	1			T40	1		T42	2		T61	2
pow[0x6]	270	1			T6	4		T40	3		T42	6
pow[0x7]	539	1			T6	7		T40	9		T42	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

212

1

T6

4

T40

1

T61

1

min

29451

1

T1

6

T3

7

T5

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29451	1			T1	6		T3	7		T5	8
pow[0x4]	1	1			T208	1		-	-		-	-
pow[0x5]	1	1			T209	1		-	-		-	-
pow[0x6]	2	1			T204	1		T210	1		-	-
pow[0x8]	4	1			T211	1		T212	1		T213	1
pow[0x9]	12	1			T61	1		T130	1		T214	2
pow[0xa]	16	1			T61	1		T203	1		T91	1
pow[0xb]	28	1			T6	1		T42	1		T203	1
pow[0xc]	69	1			T6	1		T42	2		T61	1
pow[0xd]	157	1			T6	4		T40	4		T42	3
pow[0xe]	305	1			T6	3		T40	4		T42	5
pow[0xf]	561	1			T6	7		T40	10		T42	9