Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2293	1			T6	17		T10	4		T34	2
auto[PWRUP]	141	1			T40	1		T50	3		T203	4
auto[ONEST_0]	92	1			T6	1		T40	1		T42	3
auto[ONEST_021]	16	1			T6	1		T61	1		T49	1
auto[ONEST_1]	87	1			T6	1		T42	2		T61	1
auto[ONEST_DONE]	3	1			T40	1		T130	1		T200	1
auto[LP_0]	137	1			T6	2		T40	1		T42	2
auto[LP_021]	37	1			T195	1		T130	2		T201	1
auto[LP_1]	149	1			T6	2		T42	2		T61	1
auto[LP_EVAL]	52	1			T6	2		T40	1		T42	1
auto[LP_SLP]	558	1			T6	6		T40	12		T42	6
auto[LP_PWRUP]	32	1			T6	1		T203	1		T205	1
auto[NP_0]	239	1			T6	4		T39	1		T40	2
auto[NP_021]	33	1			T39	1		T40	1		T42	1
auto[NP_1]	241	1			T6	2		T39	2		T42	3
auto[NP_EVAL]	24	1			T93	1		T130	2		T15	1
auto[NP_DONE]	1	1			T209	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T91

1

T241

1

T343

1

min

1973

1

T6

8

T10

4

T34

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1983	1			T6	8		T10	4		T34	2
pow[0x1]	18	1			T6	1		T206	1		T214	1
pow[0x2]	14	1			T47	1		T203	1		T56	1
pow[0x3]	43	1			T6	1		T40	1		T61	1
pow[0x4]	68	1			T40	1		T42	1		T50	1
pow[0x5]	130	1			T6	4		T40	1		T42	3
pow[0x6]	279	1			T6	6		T40	4		T42	1
pow[0x7]	537	1			T6	6		T40	8		T42	12

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

172

1

T6

4

T40

3

T42

4

min

1356

1

T6

4

T10

4

T34

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1359	1			T6	4		T10	4		T34	2
pow[0x1]	13	1			T14	1		T15	1		T16	1
pow[0x2]	15	1			T51	1		T242	4		T18	1
pow[0x3]	60	1			T46	3		T56	1		T57	1
pow[0x4]	48	1			T47	2		T49	2		T50	1
pow[0x7]	3	1			T93	1		T200	1		T344	1
pow[0x8]	8	1			T200	1		T345	2		T214	1
pow[0x9]	10	1			T40	1		T205	1		T94	1
pow[0xa]	18	1			T6	1		T40	1		T203	1
pow[0xb]	37	1			T40	2		T61	1		T205	1
pow[0xc]	81	1			T6	1		T58	1		T205	2
pow[0xd]	156	1			T6	1		T40	1		T42	2
pow[0xe]	289	1			T6	5		T40	6		T42	3
pow[0xf]	632	1			T6	11		T40	9		T42	8