Assert Coverage for Module :
adc_ctrl_fsm_sva
Assertion Details
FsmDebugOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31964971 |
31887223 |
0 |
0 |
T1 |
34146 |
34076 |
0 |
0 |
T2 |
1053 |
1003 |
0 |
0 |
T3 |
32843 |
32771 |
0 |
0 |
T4 |
77 |
1 |
0 |
0 |
T5 |
41235 |
41157 |
0 |
0 |
T6 |
80 |
1 |
0 |
0 |
T7 |
1143 |
1088 |
0 |
0 |
T8 |
97541 |
97491 |
0 |
0 |
T9 |
41164 |
41071 |
0 |
0 |
T10 |
40869 |
40561 |
0 |
0 |
FsmStateHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1100 |
1100 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
FsmStateSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31964971 |
6595 |
0 |
0 |
T1 |
34146 |
6 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
7 |
0 |
0 |
T5 |
41235 |
8 |
0 |
0 |
T6 |
80 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
20 |
0 |
0 |
T9 |
41164 |
6 |
0 |
0 |
T10 |
40869 |
5 |
0 |
0 |
T11 |
67826 |
17 |
0 |
0 |
T12 |
0 |
24 |
0 |
0 |
T13 |
0 |
21 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |
LpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1100 |
1100 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
LpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31964971 |
6595 |
0 |
0 |
T1 |
34146 |
6 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
7 |
0 |
0 |
T5 |
41235 |
8 |
0 |
0 |
T6 |
80 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
20 |
0 |
0 |
T9 |
41164 |
6 |
0 |
0 |
T10 |
40869 |
5 |
0 |
0 |
T11 |
67826 |
17 |
0 |
0 |
T12 |
0 |
24 |
0 |
0 |
T13 |
0 |
21 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |
NpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1100 |
1100 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
NpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31964971 |
6595 |
0 |
0 |
T1 |
34146 |
6 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
7 |
0 |
0 |
T5 |
41235 |
8 |
0 |
0 |
T6 |
80 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
20 |
0 |
0 |
T9 |
41164 |
6 |
0 |
0 |
T10 |
40869 |
5 |
0 |
0 |
T11 |
67826 |
17 |
0 |
0 |
T12 |
0 |
24 |
0 |
0 |
T13 |
0 |
21 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |
PwrupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1100 |
1100 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
PwrupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31964971 |
6595 |
0 |
0 |
T1 |
34146 |
6 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
7 |
0 |
0 |
T5 |
41235 |
8 |
0 |
0 |
T6 |
80 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
20 |
0 |
0 |
T9 |
41164 |
6 |
0 |
0 |
T10 |
40869 |
5 |
0 |
0 |
T11 |
67826 |
17 |
0 |
0 |
T12 |
0 |
24 |
0 |
0 |
T13 |
0 |
21 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |
WakeupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1100 |
1100 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
5 |
5 |
0 |
0 |
WakeupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31964971 |
6595 |
0 |
0 |
T1 |
34146 |
6 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
7 |
0 |
0 |
T5 |
41235 |
8 |
0 |
0 |
T6 |
80 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
20 |
0 |
0 |
T9 |
41164 |
6 |
0 |
0 |
T10 |
40869 |
5 |
0 |
0 |
T11 |
67826 |
17 |
0 |
0 |
T12 |
0 |
24 |
0 |
0 |
T13 |
0 |
21 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |