Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2474	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2497	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2500	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2500	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2546	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2630	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2563	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2443	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2690	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2622	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2272	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2563	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2474	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2573	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2511	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2881	0	0
adc_en_ctl_rd_A	2147483647	1979	0	0
adc_fsm_rst_rd_A	2147483647	1973	0	0
adc_intr_ctl_rd_A	2147483647	2618	0	0
adc_lp_sample_ctl_rd_A	2147483647	1989	0	0
adc_pd_ctl_rd_A	2147483647	2021	0	0
adc_sample_ctl_rd_A	2147483647	1905	0	0
adc_wakeup_ctl_rd_A	2147483647	2045	0	0
intr_enable_rd_A	2147483647	2610	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T14	164756	21	0	0
T15	0	33	0	0
T16	0	17	0	0
T17	0	20	0	0
T18	0	29	0	0
T19	0	16	0	0
T20	0	22	0	0
T21	0	37	0	0
T22	0	29	0	0
T23	0	16	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2497	0	0
T14	164756	12	0	0
T15	0	48	0	0
T16	0	18	0	0
T17	0	18	0	0
T18	0	14	0	0
T19	0	11	0	0
T20	0	7	0	0
T21	0	48	0	0
T22	0	36	0	0
T23	0	6	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2500	0	0
T14	164756	30	0	0
T15	0	23	0	0
T16	0	14	0	0
T17	0	20	0	0
T18	0	20	0	0
T19	0	12	0	0
T20	0	6	0	0
T21	0	29	0	0
T22	0	33	0	0
T23	0	11	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2500	0	0
T14	164756	24	0	0
T15	0	48	0	0
T16	0	16	0	0
T17	0	15	0	0
T18	0	23	0	0
T19	0	13	0	0
T20	0	18	0	0
T21	0	31	0	0
T22	0	39	0	0
T23	0	9	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2546	0	0
T14	164756	7	0	0
T15	0	25	0	0
T16	0	11	0	0
T17	0	23	0	0
T18	0	23	0	0
T19	0	38	0	0
T20	0	1	0	0
T21	0	43	0	0
T22	0	23	0	0
T23	0	6	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2630	0	0
T14	164756	13	0	0
T15	0	35	0	0
T16	0	18	0	0
T17	0	23	0	0
T18	0	35	0	0
T19	0	13	0	0
T20	0	13	0	0
T21	0	30	0	0
T22	0	47	0	0
T23	0	23	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2563	0	0
T14	164756	7	0	0
T15	0	27	0	0
T16	0	21	0	0
T17	0	12	0	0
T18	0	21	0	0
T19	0	22	0	0
T20	0	14	0	0
T21	0	51	0	0
T22	0	39	0	0
T23	0	8	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2443	0	0
T14	164756	18	0	0
T15	0	26	0	0
T16	0	28	0	0
T17	0	22	0	0
T18	0	12	0	0
T19	0	18	0	0
T20	0	5	0	0
T21	0	26	0	0
T22	0	37	0	0
T23	0	2	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2690	0	0
T14	164756	21	0	0
T15	0	48	0	0
T16	0	21	0	0
T17	0	24	0	0
T18	0	15	0	0
T19	0	20	0	0
T20	0	16	0	0
T21	0	35	0	0
T22	0	56	0	0
T23	0	3	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2622	0	0
T14	164756	14	0	0
T15	0	32	0	0
T16	0	12	0	0
T17	0	12	0	0
T18	0	10	0	0
T19	0	31	0	0
T20	0	10	0	0
T21	0	44	0	0
T22	0	45	0	0
T23	0	13	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2272	0	0
T14	164756	15	0	0
T15	0	34	0	0
T16	0	27	0	0
T17	0	14	0	0
T18	0	9	0	0
T19	0	4	0	0
T20	0	6	0	0
T21	0	34	0	0
T22	0	37	0	0
T23	0	9	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2563	0	0
T14	164756	14	0	0
T15	0	42	0	0
T16	0	15	0	0
T17	0	16	0	0
T18	0	14	0	0
T19	0	12	0	0
T20	0	6	0	0
T21	0	25	0	0
T22	0	38	0	0
T23	0	18	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T14	164756	32	0	0
T15	0	48	0	0
T16	0	3	0	0
T17	0	18	0	0
T18	0	9	0	0
T19	0	14	0	0
T20	0	5	0	0
T21	0	36	0	0
T22	0	39	0	0
T23	0	2	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2573	0	0
T14	164756	16	0	0
T15	0	37	0	0
T16	0	11	0	0
T17	0	21	0	0
T18	0	16	0	0
T19	0	31	0	0
T20	0	7	0	0
T21	0	41	0	0
T22	0	52	0	0
T23	0	12	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2511	0	0
T14	164756	15	0	0
T15	0	48	0	0
T16	0	25	0	0
T17	0	19	0	0
T18	0	13	0	0
T19	0	20	0	0
T20	0	15	0	0
T21	0	20	0	0
T22	0	32	0	0
T23	0	16	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2881	0	0
T14	164756	19	0	0
T15	0	34	0	0
T16	0	26	0	0
T17	0	17	0	0
T18	0	19	0	0
T19	0	33	0	0
T20	0	7	0	0
T21	0	24	0	0
T22	0	50	0	0
T23	0	16	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1979	0	0
T14	164756	17	0	0
T15	0	44	0	0
T16	0	14	0	0
T17	0	13	0	0
T18	0	13	0	0
T19	0	38	0	0
T20	0	4	0	0
T21	0	43	0	0
T22	0	29	0	0
T23	0	5	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1973	0	0
T14	164756	14	0	0
T15	0	51	0	0
T16	0	22	0	0
T17	0	18	0	0
T18	0	24	0	0
T19	0	21	0	0
T20	0	23	0	0
T21	0	23	0	0
T22	0	24	0	0
T23	0	16	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2618	0	0
T14	164756	18	0	0
T15	0	38	0	0
T16	0	14	0	0
T17	0	11	0	0
T18	0	24	0	0
T19	0	27	0	0
T20	0	9	0	0
T21	0	33	0	0
T22	0	32	0	0
T23	0	11	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1989	0	0
T14	164756	23	0	0
T15	0	40	0	0
T16	0	24	0	0
T17	0	18	0	0
T18	0	6	0	0
T19	0	10	0	0
T20	0	13	0	0
T21	0	33	0	0
T22	0	48	0	0
T23	0	8	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2021	0	0
T14	164756	20	0	0
T15	0	34	0	0
T16	0	15	0	0
T17	0	15	0	0
T18	0	18	0	0
T19	0	12	0	0
T20	0	6	0	0
T21	0	26	0	0
T22	0	27	0	0
T23	0	5	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905	0	0
T14	164756	17	0	0
T15	0	49	0	0
T16	0	9	0	0
T17	0	22	0	0
T18	0	17	0	0
T19	0	14	0	0
T21	0	30	0	0
T22	0	41	0	0
T23	0	13	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0
T33	0	12	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2045	0	0
T14	164756	25	0	0
T15	0	49	0	0
T16	0	12	0	0
T17	0	15	0	0
T18	0	23	0	0
T19	0	12	0	0
T20	0	19	0	0
T21	0	38	0	0
T22	0	28	0	0
T23	0	9	0	0
T24	257779	0	0	0
T25	372620	0	0	0
T26	71157	0	0	0
T27	857880	0	0	0
T28	811960	0	0	0
T29	448190	0	0	0
T30	379235	0	0	0
T31	6406	0	0	0
T32	123338	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2610	0	0
T14	0	28	0	0
T15	0	55	0	0
T16	0	27	0	0
T17	0	23	0	0
T18	0	25	0	0
T19	0	30	0	0
T20	0	21	0	0
T34	394193	15	0	0
T35	0	5	0	0
T36	0	57	0	0
T37	141982	0	0	0
T38	594698	0	0	0
T39	129487	0	0	0
T40	313361	0	0	0
T41	7293	0	0	0
T42	763629	0	0	0
T43	159736	0	0	0
T44	51026	0	0	0
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