Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1221848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1195535

1

T1

1402

T4

4

T2

2112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2122332	1			T1	2479		T4	1		T2	4081
values[0x0]	146914	1			T1	163		T4	8		T2	113
values[0x1]	148137	1			T1	170		T4	6		T2	134

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	978289	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1439094

1

T1

1674

T4

5

T2

2576

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6868	1			T1	7		T3	3		T7	9
valid_sources[0x01]	17657	1			T1	7		T3	2		T7	6
valid_sources[0x02]	7182	1			T1	13		T3	5		T7	4
valid_sources[0x03]	7243	1			T1	13		T3	4		T7	4
valid_sources[0x04]	11492	1			T1	17		T3	5		T7	4
valid_sources[0x05]	6861	1			T1	9		T3	6		T5	1
valid_sources[0x06]	7040	1			T1	9		T3	4		T7	2
valid_sources[0x07]	7179	1			T1	14		T3	2		T7	4
valid_sources[0x08]	7353	1			T1	13		T3	1		T7	4
valid_sources[0x09]	7048	1			T1	17		T3	3		T7	3
valid_sources[0x0a]	7040	1			T1	10		T3	1		T5	1
valid_sources[0x0b]	8750	1			T1	12		T3	5		T7	1
valid_sources[0x0c]	11304	1			T1	8		T3	1		T7	3
valid_sources[0x0d]	16634	1			T1	2		T3	8		T5	1
valid_sources[0x0e]	8586	1			T1	15		T3	2		T9	24
valid_sources[0x0f]	7124	1			T1	18		T3	5		T7	3
valid_sources[0x10]	9604	1			T1	10		T3	5		T7	1
valid_sources[0x11]	12801	1			T1	17		T3	3		T5	1
valid_sources[0x12]	8875	1			T1	6		T3	5		T5	1
valid_sources[0x13]	11690	1			T1	8		T3	8		T7	3
valid_sources[0x14]	7669	1			T1	8		T4	1		T3	2
valid_sources[0x15]	6948	1			T1	17		T3	3		T7	6
valid_sources[0x16]	11370	1			T1	30		T3	4		T7	2
valid_sources[0x17]	7202	1			T1	8		T3	3		T7	9
valid_sources[0x18]	7795	1			T3	975		T7	2		T8	2
valid_sources[0x19]	7242	1			T1	8		T3	2		T7	3
valid_sources[0x1a]	6894	1			T1	23		T3	5		T7	1
valid_sources[0x1b]	7477	1			T1	8		T3	4		T7	1
valid_sources[0x1c]	8567	1			T1	23		T3	3		T7	4
valid_sources[0x1d]	15663	1			T1	20		T3	4		T7	1
valid_sources[0x1e]	11206	1			T1	9		T7	6		T9	27
valid_sources[0x1f]	12145	1			T1	10		T3	3		T7	3
valid_sources[0x20]	6800	1			T1	5		T3	2		T7	5
valid_sources[0x21]	7006	1			T1	12		T3	2		T7	6
valid_sources[0x22]	8044	1			T1	7		T3	2		T5	1
valid_sources[0x23]	16405	1			T1	7		T3	4		T5	2
valid_sources[0x24]	7351	1			T1	7		T3	3		T9	17
valid_sources[0x25]	7707	1			T1	14		T3	4		T7	8
valid_sources[0x26]	18935	1			T1	6		T3	3		T7	3
valid_sources[0x27]	8522	1			T1	15		T3	5		T7	5
valid_sources[0x28]	11273	1			T1	11		T3	3		T5	1
valid_sources[0x29]	11198	1			T1	16		T3	8		T7	7
valid_sources[0x2a]	7369	1			T1	13		T3	5		T7	9
valid_sources[0x2b]	7393	1			T1	9		T3	8		T7	2
valid_sources[0x2c]	12605	1			T1	11		T3	9		T7	6
valid_sources[0x2d]	6843	1			T1	18		T3	12		T7	3
valid_sources[0x2e]	11297	1			T1	6		T3	2		T7	3
valid_sources[0x2f]	7413	1			T1	10		T4	1		T3	2
valid_sources[0x30]	16844	1			T1	9		T3	5		T7	3
valid_sources[0x31]	9660	1			T1	5		T3	3		T7	3
valid_sources[0x32]	6913	1			T1	12		T3	3		T7	2
valid_sources[0x33]	6836	1			T1	5		T3	5		T7	5
valid_sources[0x34]	6929	1			T1	11		T3	3		T7	5
valid_sources[0x35]	11204	1			T1	10		T3	3		T7	3
valid_sources[0x36]	8184	1			T1	12		T3	4		T7	6
valid_sources[0x37]	6845	1			T1	10		T3	5		T7	1
valid_sources[0x38]	14136	1			T1	6		T3	2		T5	1
valid_sources[0x39]	6924	1			T1	1		T3	2		T7	2
valid_sources[0x3a]	7364	1			T1	4		T4	1		T3	1
valid_sources[0x3b]	7002	1			T1	12		T3	2		T7	4
valid_sources[0x3c]	7707	1			T1	8		T4	1		T3	5
valid_sources[0x3d]	8583	1			T1	22		T3	6		T7	7
valid_sources[0x3e]	13768	1			T1	9		T3	3		T5	1
valid_sources[0x3f]	10637	1			T1	11		T3	3		T7	5
valid_sources[0x40]	7904	1			T1	3		T3	2		T7	3
valid_sources[0x41]	9726	1			T1	7		T3	4		T7	6
valid_sources[0x42]	16373	1			T1	5		T4	1		T3	5
valid_sources[0x43]	11522	1			T1	19		T3	3		T7	4
valid_sources[0x44]	7388	1			T1	16		T3	2		T7	2
valid_sources[0x45]	6948	1			T1	18		T3	1		T7	3
valid_sources[0x46]	7133	1			T1	16		T3	1		T7	5
valid_sources[0x47]	7763	1			T1	19		T3	6		T7	5
valid_sources[0x48]	7061	1			T1	11		T3	3		T7	8
valid_sources[0x49]	10958	1			T1	9		T3	4		T7	5
valid_sources[0x4a]	6693	1			T1	8		T3	8		T7	3
valid_sources[0x4b]	7487	1			T1	5		T3	4		T7	3
valid_sources[0x4c]	6981	1			T1	10		T3	1		T7	2
valid_sources[0x4d]	10755	1			T1	5		T3	4		T7	4
valid_sources[0x4e]	7212	1			T1	7		T3	4		T7	3
valid_sources[0x4f]	18199	1			T1	8		T3	5		T7	4
valid_sources[0x50]	11375	1			T1	7		T3	2		T9	7
valid_sources[0x51]	12333	1			T1	5		T3	4		T7	3
valid_sources[0x52]	11752	1			T1	14		T3	3		T7	1
valid_sources[0x53]	6773	1			T1	4		T3	3		T5	1
valid_sources[0x54]	25231	1			T1	10		T3	6		T7	4
valid_sources[0x55]	7712	1			T1	10		T3	5		T5	1
valid_sources[0x56]	6951	1			T1	17		T3	4		T7	5
valid_sources[0x57]	7248	1			T1	9		T3	3		T7	5
valid_sources[0x58]	11798	1			T1	5		T3	8		T7	3
valid_sources[0x59]	7262	1			T1	16		T3	3		T7	7
valid_sources[0x5a]	7781	1			T1	15		T3	5		T7	3
valid_sources[0x5b]	8064	1			T1	20		T3	3		T7	6
valid_sources[0x5c]	11632	1			T1	16		T3	4		T7	1
valid_sources[0x5d]	8161	1			T1	17		T3	2		T8	1
valid_sources[0x5e]	11258	1			T1	5		T3	2		T7	4
valid_sources[0x5f]	6731	1			T1	13		T3	5		T5	1
valid_sources[0x60]	7095	1			T1	17		T3	4		T7	4
valid_sources[0x61]	8206	1			T1	9		T3	2		T7	2
valid_sources[0x62]	10102	1			T1	11		T3	2		T9	22
valid_sources[0x63]	11185	1			T1	19		T3	4		T7	3
valid_sources[0x64]	13989	1			T1	38		T2	4328		T3	1
valid_sources[0x65]	6593	1			T1	7		T3	3		T7	3
valid_sources[0x66]	9863	1			T1	3		T3	3		T7	3
valid_sources[0x67]	8353	1			T1	12		T3	3		T7	2
valid_sources[0x68]	10981	1			T1	13		T3	2		T7	5
valid_sources[0x69]	9640	1			T1	20		T7	2		T8	1
valid_sources[0x6a]	6998	1			T1	15		T3	4		T7	2
valid_sources[0x6b]	8338	1			T1	12		T3	2		T7	5
valid_sources[0x6c]	8102	1			T1	5		T3	3		T7	5
valid_sources[0x6d]	10113	1			T1	7		T3	2		T5	1
valid_sources[0x6e]	6991	1			T1	7		T7	5		T9	10
valid_sources[0x6f]	6650	1			T1	7		T3	4		T7	3
valid_sources[0x70]	14967	1			T1	14		T3	8		T5	1
valid_sources[0x71]	9008	1			T1	11		T3	3		T7	3
valid_sources[0x72]	7318	1			T1	5		T3	1		T7	1
valid_sources[0x73]	7020	1			T1	8		T3	2		T7	2
valid_sources[0x74]	17496	1			T1	16		T3	4		T7	1
valid_sources[0x75]	6844	1			T1	14		T3	5		T7	3
valid_sources[0x76]	11125	1			T1	17		T3	2		T7	6
valid_sources[0x77]	7545	1			T1	19		T3	3		T7	4
valid_sources[0x78]	7715	1			T1	19		T3	2		T7	4
valid_sources[0x79]	16569	1			T1	9		T3	3		T7	3
valid_sources[0x7a]	12303	1			T3	3		T5	1		T7	5
valid_sources[0x7b]	7092	1			T1	20		T3	2		T7	6
valid_sources[0x7c]	6600	1			T1	19		T3	2		T7	1
valid_sources[0x7d]	11252	1			T1	12		T3	5		T7	3
valid_sources[0x7e]	6899	1			T1	7		T4	1		T3	3
valid_sources[0x7f]	7415	1			T1	16		T7	5		T9	18
valid_sources[0x80]	7660	1			T1	8		T3	1		T7	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1057859

1

T1

1259

T2

2010

T3

833

values[0x0]

all_enables

biggest_size

79940

1

T1

85

T4

3

T2

62

values[0x1]

all_enables

biggest_size

57736

1

T1

58

T4

1

T2

40