Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30457	1			T1	23		T2	8		T3	19
auto[PWRUP]	113	1			T44	4		T38	4		T69	2
auto[ONEST_0]	75	1			T7	2		T44	1		T70	2
auto[ONEST_021]	13	1			T63	1		T221	1		T222	1
auto[ONEST_1]	63	1			T7	2		T70	1		T60	1
auto[ONEST_DONE]	3	1			T223	1		T224	1		T225	1
auto[LP_0]	121	1			T7	1		T44	2		T70	3
auto[LP_021]	23	1			T226	1		T227	2		T228	1
auto[LP_1]	138	1			T7	1		T44	4		T70	3
auto[LP_EVAL]	65	1			T44	2		T69	1		T60	2
auto[LP_SLP]	472	1			T7	8		T44	5		T70	8
auto[LP_PWRUP]	19	1			T229	1		T230	1		T18	1
auto[NP_0]	126	1			T44	1		T70	1		T38	1
auto[NP_021]	37	1			T70	2		T38	1		T63	1
auto[NP_1]	140	1			T7	1		T44	1		T70	4
auto[NP_EVAL]	29	1			T70	2		T63	1		T226	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T70

1

T231

1

T232

1

min

29860

1

T1

23

T2

8

T3

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29863	1			T1	23		T2	8		T3	19
pow[0x1]	8	1			T233	2		T24	1		T234	1
pow[0x2]	18	1			T44	1		T223	1		T20	1
pow[0x3]	30	1			T223	2		T221	1		T66	1
pow[0x4]	56	1			T7	1		T44	1		T70	1
pow[0x5]	131	1			T7	1		T44	2		T70	4
pow[0x6]	269	1			T7	3		T70	4		T38	4
pow[0x7]	522	1			T7	8		T44	7		T70	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

192

1

T7

4

T44

1

T70

3

min

29406

1

T1

23

T2

8

T3

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29406	1			T1	23		T2	8		T3	19
pow[0x5]	1	1			T235	1		-	-		-	-
pow[0x8]	5	1			T236	1		T234	1		T237	1
pow[0x9]	10	1			T230	1		T233	1		T235	1
pow[0xa]	22	1			T70	2		T69	1		T60	1
pow[0xb]	40	1			T63	1		T238	1		T236	1
pow[0xc]	70	1			T44	1		T70	2		T38	3
pow[0xd]	163	1			T7	2		T70	4		T38	5
pow[0xe]	302	1			T7	3		T44	6		T70	6
pow[0xf]	602	1			T7	5		T44	12		T70	11