Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2271	1			T7	23		T12	5		T51	16
auto[PWRUP]	123	1			T44	4		T70	2		T38	1
auto[ONEST_0]	92	1			T7	1		T38	2		T69	1
auto[ONEST_021]	16	1			T70	1		T38	1		T52	1
auto[ONEST_1]	80	1			T7	2		T70	1		T69	3
auto[ONEST_DONE]	2	1			T221	1		T361	1		-	-
auto[LP_0]	135	1			T7	3		T44	2		T70	2
auto[LP_021]	32	1			T69	1		T63	1		T53	1
auto[LP_1]	114	1			T7	2		T44	3		T38	1
auto[LP_EVAL]	52	1			T7	2		T52	1		T60	1
auto[LP_SLP]	507	1			T7	6		T51	3		T44	12
auto[LP_PWRUP]	34	1			T7	1		T70	1		T63	1
auto[NP_0]	225	1			T7	2		T51	3		T44	1
auto[NP_021]	42	1			T7	1		T63	1		T223	1
auto[NP_1]	264	1			T7	5		T44	3		T70	1
auto[NP_EVAL]	33	1			T44	1		T52	1		T17	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T7

1

T221

1

T362

1

min

1974

1

T7

9

T12

5

T51

22

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1985	1			T7	9		T12	5		T51	22
pow[0x1]	13	1			T70	1		T223	1		T363	1
pow[0x2]	18	1			T69	1		T52	1		T226	1
pow[0x3]	31	1			T7	1		T69	1		T52	1
pow[0x4]	67	1			T7	6		T69	2		T63	1
pow[0x5]	124	1			T7	3		T44	5		T70	1
pow[0x6]	274	1			T7	9		T44	2		T70	5
pow[0x7]	471	1			T7	6		T44	3		T70	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

170

1

T7

2

T44

2

T70

2

min

1399

1

T7

3

T12

5

T51

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1411	1			T7	3		T12	5		T51	19
pow[0x1]	4	1			T319	2		T24	1		T364	1
pow[0x2]	41	1			T52	3		T53	4		T26	4
pow[0x3]	37	1			T51	1		T18	2		T123	1
pow[0x4]	71	1			T51	2		T16	2		T26	2
pow[0x5]	2	1			T223	1		T365	1		-	-
pow[0x6]	2	1			T362	1		T106	1		-	-
pow[0x8]	10	1			T38	1		T227	1		T366	1
pow[0x9]	13	1			T223	1		T229	1		T367	1
pow[0xa]	26	1			T70	1		T69	1		T63	2
pow[0xb]	35	1			T44	2		T70	2		T38	1
pow[0xc]	66	1			T7	2		T44	1		T38	1
pow[0xd]	137	1			T7	3		T44	2		T70	1
pow[0xe]	302	1			T7	8		T44	3		T70	7
pow[0xf]	573	1			T7	6		T44	8		T70	9