Assert Coverage for Module :
adc_ctrl_fsm_sva
Assertion Details
FsmDebugOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32122280 |
32040381 |
0 |
0 |
T1 |
105959 |
105888 |
0 |
0 |
T2 |
33038 |
32941 |
0 |
0 |
T3 |
71009 |
70909 |
0 |
0 |
T4 |
95 |
1 |
0 |
0 |
T5 |
5013 |
4914 |
0 |
0 |
T6 |
64474 |
64399 |
0 |
0 |
T7 |
88 |
1 |
0 |
0 |
T8 |
1225 |
1128 |
0 |
0 |
T9 |
33839 |
33739 |
0 |
0 |
T15 |
84 |
1 |
0 |
0 |
FsmStateHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1182 |
1182 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
FsmStateSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32122280 |
6526 |
0 |
0 |
T1 |
105959 |
23 |
0 |
0 |
T2 |
33038 |
8 |
0 |
0 |
T3 |
71009 |
19 |
0 |
0 |
T4 |
95 |
0 |
0 |
0 |
T5 |
5013 |
0 |
0 |
0 |
T6 |
64474 |
15 |
0 |
0 |
T7 |
88 |
0 |
0 |
0 |
T8 |
1225 |
0 |
0 |
0 |
T9 |
33839 |
6 |
0 |
0 |
T11 |
0 |
25 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
T14 |
0 |
26 |
0 |
0 |
T15 |
84 |
0 |
0 |
0 |
T54 |
0 |
16 |
0 |
0 |
LpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1182 |
1182 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
LpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32122280 |
6526 |
0 |
0 |
T1 |
105959 |
23 |
0 |
0 |
T2 |
33038 |
8 |
0 |
0 |
T3 |
71009 |
19 |
0 |
0 |
T4 |
95 |
0 |
0 |
0 |
T5 |
5013 |
0 |
0 |
0 |
T6 |
64474 |
15 |
0 |
0 |
T7 |
88 |
0 |
0 |
0 |
T8 |
1225 |
0 |
0 |
0 |
T9 |
33839 |
6 |
0 |
0 |
T11 |
0 |
25 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
T14 |
0 |
26 |
0 |
0 |
T15 |
84 |
0 |
0 |
0 |
T54 |
0 |
16 |
0 |
0 |
NpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1182 |
1182 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
NpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32122280 |
6526 |
0 |
0 |
T1 |
105959 |
23 |
0 |
0 |
T2 |
33038 |
8 |
0 |
0 |
T3 |
71009 |
19 |
0 |
0 |
T4 |
95 |
0 |
0 |
0 |
T5 |
5013 |
0 |
0 |
0 |
T6 |
64474 |
15 |
0 |
0 |
T7 |
88 |
0 |
0 |
0 |
T8 |
1225 |
0 |
0 |
0 |
T9 |
33839 |
6 |
0 |
0 |
T11 |
0 |
25 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
T14 |
0 |
26 |
0 |
0 |
T15 |
84 |
0 |
0 |
0 |
T54 |
0 |
16 |
0 |
0 |
PwrupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1182 |
1182 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
PwrupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32122280 |
6526 |
0 |
0 |
T1 |
105959 |
23 |
0 |
0 |
T2 |
33038 |
8 |
0 |
0 |
T3 |
71009 |
19 |
0 |
0 |
T4 |
95 |
0 |
0 |
0 |
T5 |
5013 |
0 |
0 |
0 |
T6 |
64474 |
15 |
0 |
0 |
T7 |
88 |
0 |
0 |
0 |
T8 |
1225 |
0 |
0 |
0 |
T9 |
33839 |
6 |
0 |
0 |
T11 |
0 |
25 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
T14 |
0 |
26 |
0 |
0 |
T15 |
84 |
0 |
0 |
0 |
T54 |
0 |
16 |
0 |
0 |
WakeupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1182 |
1182 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
WakeupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32122280 |
6526 |
0 |
0 |
T1 |
105959 |
23 |
0 |
0 |
T2 |
33038 |
8 |
0 |
0 |
T3 |
71009 |
19 |
0 |
0 |
T4 |
95 |
0 |
0 |
0 |
T5 |
5013 |
0 |
0 |
0 |
T6 |
64474 |
15 |
0 |
0 |
T7 |
88 |
0 |
0 |
0 |
T8 |
1225 |
0 |
0 |
0 |
T9 |
33839 |
6 |
0 |
0 |
T11 |
0 |
25 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T13 |
0 |
18 |
0 |
0 |
T14 |
0 |
26 |
0 |
0 |
T15 |
84 |
0 |
0 |
0 |
T54 |
0 |
16 |
0 |
0 |