Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 3 | 50.00 |
Logical | 6 | 3 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
4681698 |
0 |
0 |
T1 |
2177580 |
5224 |
0 |
0 |
T2 |
3964905 |
4878 |
0 |
0 |
T3 |
1704175 |
10245 |
0 |
0 |
T4 |
58675 |
0 |
0 |
0 |
T5 |
1253420 |
265 |
0 |
0 |
T6 |
2579030 |
9628 |
0 |
0 |
T7 |
788070 |
1547 |
0 |
0 |
T8 |
1440395 |
180 |
0 |
0 |
T9 |
812145 |
4990 |
0 |
0 |
T10 |
0 |
239 |
0 |
0 |
T11 |
0 |
14495 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
0 |
228 |
0 |
0 |
T14 |
0 |
310 |
0 |
0 |
T15 |
41160 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
178832362 |
3089825 |
0 |
0 |
T1 |
529795 |
3548 |
0 |
0 |
T2 |
165190 |
3171 |
0 |
0 |
T3 |
355045 |
6673 |
0 |
0 |
T4 |
525 |
0 |
0 |
0 |
T5 |
25065 |
179 |
0 |
0 |
T6 |
322370 |
6293 |
0 |
0 |
T7 |
112580 |
946 |
0 |
0 |
T8 |
6125 |
140 |
0 |
0 |
T9 |
169195 |
3256 |
0 |
0 |
T10 |
0 |
155 |
0 |
0 |
T11 |
0 |
9468 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
0 |
228 |
0 |
0 |
T14 |
0 |
309 |
0 |
0 |
T15 |
480 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
649913 |
0 |
0 |
T1 |
435516 |
696 |
0 |
0 |
T2 |
792981 |
697 |
0 |
0 |
T3 |
340835 |
1401 |
0 |
0 |
T4 |
11735 |
0 |
0 |
0 |
T5 |
250684 |
33 |
0 |
0 |
T6 |
515806 |
1412 |
0 |
0 |
T7 |
157614 |
246 |
0 |
0 |
T8 |
288079 |
40 |
0 |
0 |
T9 |
162429 |
711 |
0 |
0 |
T10 |
0 |
30 |
0 |
0 |
T11 |
0 |
2089 |
0 |
0 |
T15 |
8232 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35781681 |
649602 |
0 |
0 |
T1 |
105959 |
694 |
0 |
0 |
T2 |
33038 |
697 |
0 |
0 |
T3 |
71009 |
1401 |
0 |
0 |
T4 |
105 |
0 |
0 |
0 |
T5 |
5013 |
33 |
0 |
0 |
T6 |
64474 |
1412 |
0 |
0 |
T7 |
22516 |
241 |
0 |
0 |
T8 |
1225 |
40 |
0 |
0 |
T9 |
33839 |
711 |
0 |
0 |
T10 |
0 |
30 |
0 |
0 |
T11 |
0 |
2089 |
0 |
0 |
T15 |
96 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
643587 |
0 |
0 |
T1 |
435516 |
707 |
0 |
0 |
T2 |
792981 |
692 |
0 |
0 |
T3 |
340835 |
1433 |
0 |
0 |
T4 |
11735 |
0 |
0 |
0 |
T5 |
250684 |
33 |
0 |
0 |
T6 |
515806 |
1392 |
0 |
0 |
T7 |
157614 |
178 |
0 |
0 |
T8 |
288079 |
20 |
0 |
0 |
T9 |
162429 |
717 |
0 |
0 |
T10 |
0 |
30 |
0 |
0 |
T11 |
0 |
2094 |
0 |
0 |
T15 |
8232 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35781681 |
632931 |
0 |
0 |
T1 |
105959 |
692 |
0 |
0 |
T2 |
33038 |
678 |
0 |
0 |
T3 |
71009 |
1406 |
0 |
0 |
T4 |
105 |
0 |
0 |
0 |
T5 |
5013 |
33 |
0 |
0 |
T6 |
64474 |
1361 |
0 |
0 |
T7 |
22516 |
176 |
0 |
0 |
T8 |
1225 |
20 |
0 |
0 |
T9 |
33839 |
710 |
0 |
0 |
T10 |
0 |
30 |
0 |
0 |
T11 |
0 |
2054 |
0 |
0 |
T15 |
96 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
84393 |
0 |
0 |
T1 |
435516 |
113 |
0 |
0 |
T2 |
792981 |
88 |
0 |
0 |
T3 |
340835 |
202 |
0 |
0 |
T4 |
11735 |
0 |
0 |
0 |
T5 |
250684 |
0 |
0 |
0 |
T6 |
515806 |
186 |
0 |
0 |
T7 |
157614 |
1 |
0 |
0 |
T8 |
288079 |
0 |
0 |
0 |
T9 |
162429 |
98 |
0 |
0 |
T11 |
0 |
271 |
0 |
0 |
T12 |
0 |
80 |
0 |
0 |
T13 |
0 |
184 |
0 |
0 |
T14 |
0 |
260 |
0 |
0 |
T15 |
8232 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35781681 |
83637 |
0 |
0 |
T1 |
105959 |
112 |
0 |
0 |
T2 |
33038 |
88 |
0 |
0 |
T3 |
71009 |
202 |
0 |
0 |
T4 |
105 |
0 |
0 |
0 |
T5 |
5013 |
0 |
0 |
0 |
T6 |
64474 |
186 |
0 |
0 |
T7 |
22516 |
1 |
0 |
0 |
T8 |
1225 |
0 |
0 |
0 |
T9 |
33839 |
98 |
0 |
0 |
T11 |
0 |
271 |
0 |
0 |
T12 |
0 |
80 |
0 |
0 |
T13 |
0 |
184 |
0 |
0 |
T14 |
0 |
259 |
0 |
0 |
T15 |
96 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
3286424 |
0 |
0 |
T1 |
435516 |
3673 |
0 |
0 |
T2 |
792981 |
3385 |
0 |
0 |
T3 |
340835 |
7150 |
0 |
0 |
T4 |
11735 |
0 |
0 |
0 |
T5 |
250684 |
199 |
0 |
0 |
T6 |
515806 |
6599 |
0 |
0 |
T7 |
157614 |
1120 |
0 |
0 |
T8 |
288079 |
120 |
0 |
0 |
T9 |
162429 |
3456 |
0 |
0 |
T10 |
0 |
179 |
0 |
0 |
T11 |
0 |
9987 |
0 |
0 |
T15 |
8232 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35781681 |
1706277 |
0 |
0 |
T1 |
105959 |
2015 |
0 |
0 |
T2 |
33038 |
1692 |
0 |
0 |
T3 |
71009 |
3605 |
0 |
0 |
T4 |
105 |
0 |
0 |
0 |
T5 |
5013 |
113 |
0 |
0 |
T6 |
64474 |
3295 |
0 |
0 |
T7 |
22516 |
526 |
0 |
0 |
T8 |
1225 |
80 |
0 |
0 |
T9 |
33839 |
1729 |
0 |
0 |
T10 |
0 |
95 |
0 |
0 |
T11 |
0 |
5000 |
0 |
0 |
T15 |
96 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T4,T2 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T2 |
0 |
Covered |
T1,T4,T2 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17381 |
0 |
0 |
T1 |
435516 |
35 |
0 |
0 |
T2 |
792981 |
16 |
0 |
0 |
T3 |
340835 |
59 |
0 |
0 |
T4 |
11735 |
0 |
0 |
0 |
T5 |
250684 |
0 |
0 |
0 |
T6 |
515806 |
39 |
0 |
0 |
T7 |
157614 |
2 |
0 |
0 |
T8 |
288079 |
0 |
0 |
0 |
T9 |
162429 |
8 |
0 |
0 |
T11 |
0 |
54 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T13 |
0 |
44 |
0 |
0 |
T14 |
0 |
50 |
0 |
0 |
T15 |
8232 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35705638 |
17378 |
0 |
0 |
T1 |
105959 |
35 |
0 |
0 |
T2 |
33038 |
16 |
0 |
0 |
T3 |
71009 |
59 |
0 |
0 |
T4 |
105 |
0 |
0 |
0 |
T5 |
5013 |
0 |
0 |
0 |
T6 |
64474 |
39 |
0 |
0 |
T7 |
22516 |
2 |
0 |
0 |
T8 |
1225 |
0 |
0 |
0 |
T9 |
33839 |
8 |
0 |
0 |
T11 |
0 |
54 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T13 |
0 |
44 |
0 |
0 |
T14 |
0 |
50 |
0 |
0 |
T15 |
96 |
0 |
0 |
0 |