Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1816	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1616	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1709	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1688	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1633	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1636	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1621	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1772	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1760	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1572	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1515	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1685	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1676	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1723	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1601	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1727	0	0
adc_en_ctl_rd_A	2147483647	1378	0	0
adc_fsm_rst_rd_A	2147483647	1166	0	0
adc_intr_ctl_rd_A	2147483647	2033	0	0
adc_lp_sample_ctl_rd_A	2147483647	1139	0	0
adc_pd_ctl_rd_A	2147483647	1449	0	0
adc_sample_ctl_rd_A	2147483647	1197	0	0
adc_wakeup_ctl_rd_A	2147483647	1324	0	0
intr_enable_rd_A	2147483647	2260	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1816	0	0
T16	111025	16	0	0
T17	0	43	0	0
T18	0	45	0	0
T19	0	5	0	0
T20	0	26	0	0
T21	0	14	0	0
T22	0	44	0	0
T23	0	31	0	0
T24	0	33	0	0
T25	0	30	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1616	0	0
T16	111025	23	0	0
T17	0	35	0	0
T18	0	58	0	0
T19	0	3	0	0
T20	0	40	0	0
T21	0	10	0	0
T22	0	41	0	0
T23	0	36	0	0
T24	0	38	0	0
T25	0	33	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1709	0	0
T16	111025	26	0	0
T17	0	25	0	0
T18	0	34	0	0
T19	0	1	0	0
T20	0	23	0	0
T21	0	9	0	0
T22	0	32	0	0
T23	0	33	0	0
T24	0	44	0	0
T25	0	46	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1688	0	0
T16	111025	12	0	0
T17	0	23	0	0
T18	0	53	0	0
T19	0	5	0	0
T20	0	22	0	0
T21	0	1	0	0
T22	0	36	0	0
T23	0	46	0	0
T24	0	36	0	0
T25	0	56	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1633	0	0
T16	111025	26	0	0
T17	0	52	0	0
T18	0	42	0	0
T19	0	9	0	0
T20	0	36	0	0
T21	0	15	0	0
T22	0	56	0	0
T23	0	40	0	0
T24	0	14	0	0
T25	0	50	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1636	0	0
T16	111025	16	0	0
T17	0	31	0	0
T18	0	26	0	0
T19	0	10	0	0
T20	0	43	0	0
T21	0	13	0	0
T22	0	33	0	0
T23	0	47	0	0
T24	0	28	0	0
T25	0	22	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1621	0	0
T16	111025	19	0	0
T17	0	34	0	0
T18	0	41	0	0
T19	0	11	0	0
T20	0	32	0	0
T21	0	13	0	0
T22	0	35	0	0
T23	0	28	0	0
T24	0	36	0	0
T25	0	34	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1772	0	0
T16	111025	15	0	0
T17	0	40	0	0
T18	0	42	0	0
T19	0	23	0	0
T20	0	13	0	0
T21	0	2	0	0
T22	0	34	0	0
T23	0	34	0	0
T24	0	21	0	0
T25	0	43	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T16	111025	25	0	0
T17	0	44	0	0
T18	0	26	0	0
T19	0	10	0	0
T20	0	36	0	0
T21	0	20	0	0
T22	0	40	0	0
T23	0	31	0	0
T24	0	19	0	0
T25	0	40	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1572	0	0
T16	111025	15	0	0
T17	0	28	0	0
T18	0	22	0	0
T19	0	3	0	0
T20	0	29	0	0
T21	0	4	0	0
T22	0	31	0	0
T23	0	50	0	0
T24	0	31	0	0
T25	0	46	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1515	0	0
T16	111025	23	0	0
T17	0	28	0	0
T18	0	28	0	0
T19	0	6	0	0
T20	0	41	0	0
T21	0	13	0	0
T22	0	34	0	0
T23	0	52	0	0
T24	0	20	0	0
T25	0	39	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1685	0	0
T16	111025	23	0	0
T17	0	31	0	0
T18	0	36	0	0
T19	0	3	0	0
T20	0	31	0	0
T21	0	15	0	0
T22	0	27	0	0
T23	0	36	0	0
T24	0	21	0	0
T25	0	47	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1676	0	0
T16	111025	28	0	0
T17	0	50	0	0
T18	0	36	0	0
T19	0	13	0	0
T20	0	33	0	0
T21	0	7	0	0
T22	0	32	0	0
T23	0	42	0	0
T24	0	21	0	0
T25	0	39	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1723	0	0
T16	111025	21	0	0
T17	0	42	0	0
T18	0	31	0	0
T19	0	13	0	0
T20	0	40	0	0
T21	0	10	0	0
T22	0	37	0	0
T23	0	37	0	0
T24	0	32	0	0
T25	0	41	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1601	0	0
T16	111025	35	0	0
T17	0	53	0	0
T18	0	36	0	0
T19	0	1	0	0
T20	0	33	0	0
T21	0	2	0	0
T22	0	49	0	0
T23	0	18	0	0
T24	0	27	0	0
T25	0	25	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1727	0	0
T16	111025	25	0	0
T17	0	37	0	0
T18	0	37	0	0
T19	0	12	0	0
T20	0	26	0	0
T21	0	21	0	0
T22	0	28	0	0
T23	0	37	0	0
T24	0	20	0	0
T25	0	31	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1378	0	0
T16	111025	14	0	0
T17	0	26	0	0
T18	0	55	0	0
T19	0	12	0	0
T20	0	27	0	0
T21	0	23	0	0
T22	0	51	0	0
T23	0	33	0	0
T24	0	14	0	0
T25	0	38	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1166	0	0
T16	111025	18	0	0
T17	0	33	0	0
T18	0	31	0	0
T19	0	8	0	0
T20	0	43	0	0
T21	0	9	0	0
T22	0	30	0	0
T23	0	53	0	0
T24	0	16	0	0
T25	0	35	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T16	111025	19	0	0
T17	0	42	0	0
T18	0	61	0	0
T19	0	14	0	0
T20	0	45	0	0
T21	0	7	0	0
T22	0	38	0	0
T23	0	41	0	0
T24	0	43	0	0
T25	0	21	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1139	0	0
T16	111025	19	0	0
T17	0	30	0	0
T18	0	36	0	0
T19	0	2	0	0
T20	0	42	0	0
T21	0	2	0	0
T22	0	43	0	0
T23	0	42	0	0
T24	0	41	0	0
T25	0	23	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449	0	0
T16	111025	23	0	0
T17	0	27	0	0
T18	0	24	0	0
T19	0	5	0	0
T20	0	26	0	0
T21	0	5	0	0
T22	0	24	0	0
T23	0	38	0	0
T24	0	24	0	0
T25	0	34	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1197	0	0
T16	111025	19	0	0
T17	0	33	0	0
T18	0	36	0	0
T20	0	39	0	0
T22	0	30	0	0
T23	0	39	0	0
T24	0	26	0	0
T25	0	34	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0
T35	0	5	0	0
T36	0	3	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1324	0	0
T16	111025	14	0	0
T17	0	44	0	0
T18	0	29	0	0
T19	0	12	0	0
T20	0	26	0	0
T21	0	7	0	0
T22	0	42	0	0
T23	0	21	0	0
T24	0	18	0	0
T25	0	34	0	0
T26	483532	0	0	0
T27	578195	0	0	0
T28	329257	0	0	0
T29	164882	0	0	0
T30	296920	0	0	0
T31	501278	0	0	0
T32	139629	0	0	0
T33	242492	0	0	0
T34	334884	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2260	0	0
T16	0	56	0	0
T17	0	65	0	0
T18	0	66	0	0
T19	0	16	0	0
T20	0	46	0	0
T37	169186	17	0	0
T38	0	3	0	0
T39	0	6	0	0
T40	0	13	0	0
T41	0	33	0	0
T42	573662	0	0	0
T43	988644	0	0	0
T44	223257	0	0	0
T45	394178	0	0	0
T46	373726	0	0	0
T47	111233	0	0	0
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