Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1158554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1135265

1

T1

31

T2

633

T3

2129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2005989	1			T2	864		T3	4034		T4	8145
values[0x0]	143849	1			T1	33		T2	162		T3	128
values[0x1]	143981	1			T1	28		T2	193		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	928546	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1365273

1

T1

40

T2

759

T3

2566

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6399	1			T2	3		T3	31		T4	22
valid_sources[0x01]	6335	1			T2	5		T3	22		T4	33
valid_sources[0x02]	6778	1			T2	2		T3	35		T4	37
valid_sources[0x03]	7361	1			T2	3		T3	6		T4	37
valid_sources[0x04]	10579	1			T2	11		T3	21		T4	28
valid_sources[0x05]	7523	1			T2	4		T3	9		T4	39
valid_sources[0x06]	11843	1			T3	40		T4	27		T5	4
valid_sources[0x07]	7499	1			T2	1		T4	38		T8	37
valid_sources[0x08]	6542	1			T2	3		T3	16		T4	35
valid_sources[0x09]	7533	1			T2	2		T3	10		T4	32
valid_sources[0x0a]	6879	1			T2	4		T3	14		T4	26
valid_sources[0x0b]	22108	1			T2	2		T3	11		T4	32
valid_sources[0x0c]	10830	1			T2	1		T3	25		T4	47
valid_sources[0x0d]	7463	1			T2	5		T3	22		T4	30
valid_sources[0x0e]	9454	1			T2	3		T3	35		T4	26
valid_sources[0x0f]	11706	1			T2	5		T3	29		T4	41
valid_sources[0x10]	10373	1			T3	35		T4	26		T5	1
valid_sources[0x11]	6385	1			T2	7		T3	4		T4	28
valid_sources[0x12]	6383	1			T2	4		T3	17		T4	44
valid_sources[0x13]	12991	1			T1	61		T2	3		T3	15
valid_sources[0x14]	11863	1			T2	6		T3	9		T4	31
valid_sources[0x15]	11689	1			T2	6		T3	8		T4	19
valid_sources[0x16]	25173	1			T2	4		T3	11		T4	22
valid_sources[0x17]	12219	1			T3	12		T4	35		T5	3
valid_sources[0x18]	6775	1			T2	5		T3	21		T4	33
valid_sources[0x19]	6495	1			T2	2		T3	3		T4	51
valid_sources[0x1a]	10875	1			T2	6		T3	14		T4	34
valid_sources[0x1b]	10940	1			T2	4		T3	12		T4	31
valid_sources[0x1c]	9644	1			T2	2		T3	3		T4	36
valid_sources[0x1d]	6999	1			T2	2		T3	22		T4	32
valid_sources[0x1e]	8457	1			T2	12		T3	5		T4	26
valid_sources[0x1f]	10581	1			T2	7		T3	19		T4	26
valid_sources[0x20]	7348	1			T2	5		T3	8		T4	28
valid_sources[0x21]	6568	1			T2	5		T3	19		T4	31
valid_sources[0x22]	10807	1			T2	4		T3	38		T4	21
valid_sources[0x23]	8135	1			T2	7		T3	10		T4	26
valid_sources[0x24]	6382	1			T2	1		T3	6		T4	32
valid_sources[0x25]	7786	1			T2	2		T3	20		T4	25
valid_sources[0x26]	9255	1			T2	6		T3	18		T4	30
valid_sources[0x27]	9562	1			T2	6		T3	33		T4	22
valid_sources[0x28]	6420	1			T2	3		T3	59		T4	31
valid_sources[0x29]	7047	1			T2	2		T3	20		T4	33
valid_sources[0x2a]	11151	1			T2	3		T3	17		T4	30
valid_sources[0x2b]	10833	1			T2	6		T3	31		T4	17
valid_sources[0x2c]	7409	1			T2	5		T3	6		T4	42
valid_sources[0x2d]	6561	1			T2	2		T3	3		T4	28
valid_sources[0x2e]	8755	1			T2	1		T3	2		T4	31
valid_sources[0x2f]	15365	1			T2	4		T3	2		T4	48
valid_sources[0x30]	7747	1			T2	8		T3	7		T4	50
valid_sources[0x31]	6677	1			T2	3		T3	20		T4	33
valid_sources[0x32]	6565	1			T2	4		T3	15		T4	45
valid_sources[0x33]	19640	1			T2	4		T3	7		T4	33
valid_sources[0x34]	15471	1			T2	3		T3	27		T4	33
valid_sources[0x35]	13228	1			T2	2		T3	6		T4	32
valid_sources[0x36]	6183	1			T2	4		T4	28		T5	2
valid_sources[0x37]	6395	1			T2	4		T3	2		T4	31
valid_sources[0x38]	6769	1			T2	4		T3	38		T4	35
valid_sources[0x39]	11052	1			T2	2		T3	17		T4	44
valid_sources[0x3a]	7665	1			T2	4		T3	26		T4	16
valid_sources[0x3b]	10123	1			T2	1		T3	10		T4	41
valid_sources[0x3c]	10199	1			T2	2		T3	11		T4	14
valid_sources[0x3d]	6821	1			T2	4		T3	27		T4	35
valid_sources[0x3e]	6369	1			T2	2		T3	20		T4	36
valid_sources[0x3f]	11433	1			T2	5		T3	21		T4	28
valid_sources[0x40]	7467	1			T2	1		T3	31		T4	21
valid_sources[0x41]	8328	1			T2	4		T3	22		T4	25
valid_sources[0x42]	7565	1			T2	6		T3	20		T4	44
valid_sources[0x43]	7670	1			T2	2		T3	21		T4	49
valid_sources[0x44]	6826	1			T2	3		T3	7		T4	28
valid_sources[0x45]	10766	1			T2	6		T3	22		T4	22
valid_sources[0x46]	9439	1			T2	2		T3	30		T4	27
valid_sources[0x47]	9262	1			T2	5		T3	6		T4	23
valid_sources[0x48]	6716	1			T2	3		T3	15		T4	39
valid_sources[0x49]	10742	1			T2	4		T3	20		T4	42
valid_sources[0x4a]	11079	1			T2	1		T3	22		T4	36
valid_sources[0x4b]	6410	1			T2	3		T3	22		T4	40
valid_sources[0x4c]	6929	1			T2	3		T3	33		T4	27
valid_sources[0x4d]	10189	1			T2	9		T3	12		T4	33
valid_sources[0x4e]	15024	1			T3	6		T4	46		T5	2
valid_sources[0x4f]	10930	1			T2	3		T3	49		T4	48
valid_sources[0x50]	7725	1			T2	4		T3	31		T4	26
valid_sources[0x51]	6319	1			T2	5		T3	51		T4	42
valid_sources[0x52]	14939	1			T2	4		T3	27		T4	60
valid_sources[0x53]	9725	1			T2	8		T3	23		T4	36
valid_sources[0x54]	8429	1			T2	3		T3	20		T4	56
valid_sources[0x55]	6277	1			T2	3		T3	51		T4	25
valid_sources[0x56]	7844	1			T2	2		T3	5		T4	27
valid_sources[0x57]	6596	1			T2	1		T3	8		T4	24
valid_sources[0x58]	9425	1			T2	2		T3	4		T4	44
valid_sources[0x59]	11364	1			T2	5		T3	7		T4	40
valid_sources[0x5a]	6525	1			T2	4		T3	12		T4	35
valid_sources[0x5b]	6603	1			T2	4		T3	2		T4	15
valid_sources[0x5c]	9584	1			T2	1		T3	29		T4	37
valid_sources[0x5d]	6843	1			T2	1		T3	27		T4	27
valid_sources[0x5e]	9417	1			T2	2		T3	22		T4	34
valid_sources[0x5f]	7530	1			T2	2		T3	29		T4	34
valid_sources[0x60]	6972	1			T2	2		T3	1		T4	42
valid_sources[0x61]	7127	1			T2	3		T3	4		T4	26
valid_sources[0x62]	9794	1			T2	4		T3	4		T4	41
valid_sources[0x63]	20635	1			T2	14		T3	11		T4	30
valid_sources[0x64]	6689	1			T2	4		T3	8		T4	36
valid_sources[0x65]	11039	1			T2	1		T3	50		T4	31
valid_sources[0x66]	11120	1			T2	5		T3	5		T4	22
valid_sources[0x67]	12110	1			T2	3		T3	35		T4	43
valid_sources[0x68]	15521	1			T2	1		T3	4		T4	35
valid_sources[0x69]	6833	1			T2	173		T3	16		T4	28
valid_sources[0x6a]	9291	1			T2	6		T3	14		T4	50
valid_sources[0x6b]	6725	1			T3	20		T4	28		T8	92
valid_sources[0x6c]	7597	1			T2	2		T3	1		T4	22
valid_sources[0x6d]	11117	1			T2	3		T3	43		T4	31
valid_sources[0x6e]	6764	1			T2	10		T4	51		T5	2
valid_sources[0x6f]	6434	1			T2	5		T3	3		T4	26
valid_sources[0x70]	12231	1			T2	2		T3	33		T4	47
valid_sources[0x71]	7360	1			T2	2		T3	27		T4	52
valid_sources[0x72]	7000	1			T2	2		T4	33		T5	3
valid_sources[0x73]	7787	1			T2	5		T3	14		T4	42
valid_sources[0x74]	7305	1			T2	1		T3	15		T4	25
valid_sources[0x75]	6839	1			T2	2		T4	28		T5	4
valid_sources[0x76]	6558	1			T2	4		T3	8		T4	22
valid_sources[0x77]	10871	1			T3	11		T4	29		T8	66
valid_sources[0x78]	9308	1			T2	2		T3	42		T4	36
valid_sources[0x79]	7332	1			T2	5		T4	38		T5	3
valid_sources[0x7a]	6689	1			T2	2		T3	5		T4	34
valid_sources[0x7b]	9596	1			T2	2		T4	33		T5	2
valid_sources[0x7c]	6790	1			T2	5		T3	50		T4	44
valid_sources[0x7d]	7094	1			T2	8		T3	3		T4	24
valid_sources[0x7e]	10427	1			T2	2		T4	23		T5	8
valid_sources[0x7f]	10945	1			T2	3		T4	29		T7	1
valid_sources[0x80]	11476	1			T2	5		T3	1		T4	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

999516

1

T2

427

T3

2030

T4

4060

values[0x0]

all_enables

biggest_size

78937

1

T1

16

T2

102

T3

62

values[0x1]

all_enables

biggest_size

56812

1

T1

15

T2

104

T3

37