Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28114	1			T3	10		T4	16		T5	22
auto[PWRUP]	122	1			T56	2		T198	2		T199	3
auto[ONEST_0]	59	1			T56	2		T57	1		T29	1
auto[ONEST_021]	16	1			T57	1		T29	1		T199	1
auto[ONEST_1]	77	1			T41	1		T56	1		T57	3
auto[ONEST_DONE]	11	1			T200	1		T48	2		T201	1
auto[LP_0]	112	1			T57	4		T29	3		T198	1
auto[LP_021]	35	1			T41	1		T56	1		T57	1
auto[LP_1]	119	1			T41	2		T56	2		T57	1
auto[LP_EVAL]	67	1			T57	1		T198	1		T199	2
auto[LP_SLP]	496	1			T41	2		T56	6		T57	9
auto[LP_PWRUP]	23	1			T29	1		T198	1		T202	1
auto[NP_0]	156	1			T41	3		T56	2		T57	2
auto[NP_021]	31	1			T56	1		T57	2		T29	1
auto[NP_1]	156	1			T41	1		T56	2		T57	3
auto[NP_EVAL]	41	1			T56	1		T57	2		T203	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T198

1

T204

1

T205

1

min

27615

1

T3

10

T4

16

T5

22

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27624	1			T3	10		T4	16		T5	22
pow[0x1]	14	1			T198	1		T203	1		T200	1
pow[0x2]	23	1			T56	1		T57	1		T199	1
pow[0x3]	35	1			T41	1		T56	1		T198	2
pow[0x4]	47	1			T56	2		T57	1		T29	2
pow[0x5]	121	1			T41	1		T56	2		T29	1
pow[0x6]	265	1			T41	2		T56	3		T57	1
pow[0x7]	516	1			T41	2		T56	4		T57	14

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T41

1

T56

4

T57

5

min

27183

1

T3

10

T4

16

T5

22

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27184	1			T3	10		T4	16		T5	22
pow[0x5]	2	1			T206	1		T207	1		-	-
pow[0x6]	1	1			T205	1		-	-		-	-
pow[0x7]	4	1			T208	1		T209	1		T210	1
pow[0x8]	2	1			T211	1		T212	1		-	-
pow[0x9]	8	1			T199	1		T203	1		T213	1
pow[0xa]	22	1			T29	2		T214	2		T200	1
pow[0xb]	32	1			T57	1		T29	2		T198	1
pow[0xc]	59	1			T57	1		T15	1		T29	2
pow[0xd]	147	1			T41	2		T56	1		T57	4
pow[0xe]	270	1			T41	5		T56	5		T57	2
pow[0xf]	531	1			T41	3		T56	3		T57	10