Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2182	1			T2	13		T7	4		T41	12
auto[PWRUP]	135	1			T2	1		T41	1		T57	2
auto[ONEST_0]	89	1			T56	1		T57	1		T15	1
auto[ONEST_021]	21	1			T2	1		T57	1		T198	1
auto[ONEST_1]	87	1			T56	3		T29	4		T43	1
auto[ONEST_DONE]	1	1			T342	1		-	-		-	-
auto[LP_0]	134	1			T41	4		T56	3		T15	1
auto[LP_021]	28	1			T41	1		T214	1		T45	1
auto[LP_1]	140	1			T41	1		T56	1		T57	3
auto[LP_EVAL]	59	1			T41	1		T56	1		T57	1
auto[LP_SLP]	500	1			T41	7		T56	10		T57	7
auto[LP_PWRUP]	30	1			T2	1		T57	1		T42	1
auto[NP_0]	210	1			T2	2		T40	2		T57	4
auto[NP_021]	56	1			T2	1		T41	1		T56	1
auto[NP_1]	208	1			T2	1		T41	2		T56	2
auto[NP_EVAL]	23	1			T2	1		T343	1		T204	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T202

1

T157

1

T344

1

min

1915

1

T2

20

T7

4

T41

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1926	1			T2	20		T7	4		T41	10
pow[0x1]	20	1			T202	1		T45	1		T141	1
pow[0x2]	21	1			T57	1		T29	1		T203	2
pow[0x3]	26	1			T57	1		T199	1		T204	1
pow[0x4]	65	1			T2	1		T41	1		T56	1
pow[0x5]	150	1			T41	3		T56	1		T57	3
pow[0x6]	217	1			T41	2		T56	3		T57	4
pow[0x7]	478	1			T41	5		T56	7		T57	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

175

1

T56

5

T57

1

T29

1

min

1349

1

T2

15

T7

4

T41

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1357	1			T2	15		T7	4		T41	1
pow[0x1]	16	1			T2	1		T43	1		T46	2
pow[0x2]	24	1			T40	2		T42	5		T46	1
pow[0x3]	42	1			T2	4		T15	4		T44	1
pow[0x4]	36	1			T43	2		T199	1		T44	1
pow[0x5]	1	1			T345	1		-	-		-	-
pow[0x6]	1	1			T304	1		-	-		-	-
pow[0x7]	2	1			T346	1		T347	1		-	-
pow[0x8]	7	1			T141	2		T201	1		T60	1
pow[0x9]	13	1			T56	1		T15	1		T200	1
pow[0xa]	23	1			T29	1		T198	1		T199	1
pow[0xb]	34	1			T41	2		T198	2		T199	2
pow[0xc]	65	1			T41	1		T56	1		T57	1
pow[0xd]	163	1			T41	2		T56	3		T57	3
pow[0xe]	280	1			T2	1		T41	5		T56	2
pow[0xf]	563	1			T41	9		T56	7		T57	8