Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2286	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2147	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2460	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2232	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2447	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2200	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2225	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2159	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2329	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2301	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2275	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2285	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2301	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2287	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2140	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2512	0	0
adc_en_ctl_rd_A	2147483647	1773	0	0
adc_fsm_rst_rd_A	2147483647	1539	0	0
adc_intr_ctl_rd_A	2147483647	2259	0	0
adc_lp_sample_ctl_rd_A	2147483647	1616	0	0
adc_pd_ctl_rd_A	2147483647	1940	0	0
adc_sample_ctl_rd_A	2147483647	1668	0	0
adc_wakeup_ctl_rd_A	2147483647	1929	0	0
intr_enable_rd_A	2147483647	2353	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2286	0	0
T15	362622	17	0	0
T16	0	30	0	0
T17	0	15	0	0
T18	0	36	0	0
T19	0	53	0	0
T20	0	21	0	0
T21	0	4	0	0
T22	0	9	0	0
T23	0	11	0	0
T24	0	41	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147	0	0
T15	362622	50	0	0
T16	0	12	0	0
T17	0	17	0	0
T18	0	37	0	0
T19	0	34	0	0
T20	0	33	0	0
T21	0	22	0	0
T22	0	16	0	0
T23	0	24	0	0
T24	0	61	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2460	0	0
T15	362622	25	0	0
T16	0	11	0	0
T17	0	13	0	0
T18	0	42	0	0
T19	0	49	0	0
T20	0	11	0	0
T21	0	5	0	0
T22	0	8	0	0
T23	0	8	0	0
T24	0	71	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2232	0	0
T15	362622	50	0	0
T16	0	9	0	0
T17	0	18	0	0
T18	0	21	0	0
T19	0	31	0	0
T20	0	9	0	0
T21	0	17	0	0
T22	0	35	0	0
T23	0	13	0	0
T24	0	17	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2447	0	0
T15	362622	25	0	0
T16	0	19	0	0
T17	0	2	0	0
T18	0	33	0	0
T19	0	63	0	0
T20	0	5	0	0
T21	0	35	0	0
T22	0	31	0	0
T23	0	24	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	4	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2200	0	0
T15	362622	32	0	0
T16	0	15	0	0
T17	0	11	0	0
T18	0	31	0	0
T19	0	51	0	0
T20	0	33	0	0
T21	0	6	0	0
T22	0	18	0	0
T23	0	8	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	13	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T15	362622	35	0	0
T16	0	23	0	0
T17	0	8	0	0
T18	0	23	0	0
T19	0	49	0	0
T20	0	10	0	0
T21	0	30	0	0
T22	0	9	0	0
T23	0	23	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	39	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159	0	0
T15	362622	25	0	0
T16	0	19	0	0
T17	0	9	0	0
T18	0	20	0	0
T19	0	36	0	0
T20	0	21	0	0
T21	0	4	0	0
T22	0	26	0	0
T23	0	17	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	13	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2329	0	0
T15	362622	22	0	0
T16	0	29	0	0
T17	0	17	0	0
T18	0	27	0	0
T19	0	46	0	0
T20	0	33	0	0
T21	0	19	0	0
T22	0	11	0	0
T23	0	19	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	23	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2301	0	0
T15	362622	36	0	0
T16	0	9	0	0
T17	0	22	0	0
T18	0	45	0	0
T19	0	26	0	0
T20	0	5	0	0
T21	0	24	0	0
T22	0	3	0	0
T23	0	13	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	19	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2275	0	0
T15	362622	35	0	0
T16	0	16	0	0
T17	0	12	0	0
T18	0	9	0	0
T19	0	36	0	0
T20	0	40	0	0
T21	0	15	0	0
T22	0	35	0	0
T23	0	17	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	17	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2285	0	0
T15	362622	23	0	0
T16	0	24	0	0
T17	0	12	0	0
T18	0	42	0	0
T19	0	30	0	0
T20	0	19	0	0
T21	0	6	0	0
T22	0	11	0	0
T23	0	11	0	0
T24	0	68	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2301	0	0
T15	362622	27	0	0
T16	0	19	0	0
T17	0	7	0	0
T18	0	27	0	0
T19	0	29	0	0
T20	0	3	0	0
T21	0	11	0	0
T22	0	23	0	0
T23	0	5	0	0
T24	0	38	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T15	362622	30	0	0
T16	0	30	0	0
T17	0	16	0	0
T18	0	34	0	0
T19	0	44	0	0
T20	0	18	0	0
T21	0	6	0	0
T22	0	14	0	0
T23	0	14	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	8	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2140	0	0
T15	362622	21	0	0
T16	0	6	0	0
T17	0	15	0	0
T18	0	30	0	0
T19	0	34	0	0
T20	0	21	0	0
T21	0	20	0	0
T22	0	20	0	0
T23	0	24	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	25	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2512	0	0
T15	362622	31	0	0
T16	0	27	0	0
T17	0	24	0	0
T18	0	53	0	0
T19	0	51	0	0
T20	0	17	0	0
T21	0	45	0	0
T22	0	11	0	0
T23	0	4	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	6	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1773	0	0
T15	362622	20	0	0
T16	0	11	0	0
T17	0	13	0	0
T18	0	18	0	0
T19	0	52	0	0
T20	0	37	0	0
T21	0	3	0	0
T22	0	7	0	0
T23	0	12	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	9	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1539	0	0
T15	362622	17	0	0
T16	0	13	0	0
T17	0	14	0	0
T18	0	22	0	0
T19	0	36	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	7	0	0
T24	0	36	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	20	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2259	0	0
T15	362622	39	0	0
T16	0	29	0	0
T17	0	23	0	0
T18	0	30	0	0
T19	0	42	0	0
T20	0	7	0	0
T21	0	19	0	0
T22	0	2	0	0
T23	0	10	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	4	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1616	0	0
T15	362622	28	0	0
T16	0	12	0	0
T17	0	17	0	0
T18	0	36	0	0
T19	0	47	0	0
T20	0	7	0	0
T21	0	5	0	0
T22	0	2	0	0
T23	0	7	0	0
T24	0	72	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T15	362622	42	0	0
T16	0	29	0	0
T17	0	11	0	0
T18	0	35	0	0
T19	0	42	0	0
T20	0	15	0	0
T21	0	10	0	0
T22	0	13	0	0
T23	0	4	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	9	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1668	0	0
T15	362622	20	0	0
T16	0	23	0	0
T17	0	11	0	0
T18	0	40	0	0
T19	0	36	0	0
T20	0	44	0	0
T21	0	10	0	0
T22	0	3	0	0
T23	0	8	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	17	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1929	0	0
T15	362622	36	0	0
T16	0	31	0	0
T17	0	18	0	0
T18	0	39	0	0
T19	0	39	0	0
T20	0	29	0	0
T21	0	11	0	0
T22	0	13	0	0
T23	0	15	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T34	0	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2353	0	0
T15	362622	22	0	0
T16	0	53	0	0
T17	0	8	0	0
T18	0	42	0	0
T19	0	39	0	0
T25	253726	0	0	0
T26	310190	0	0	0
T27	766697	0	0	0
T28	540102	0	0	0
T29	101324	0	0	0
T30	118890	0	0	0
T31	107452	0	0	0
T32	164312	0	0	0
T33	362623	0	0	0
T35	0	42	0	0
T36	0	15	0	0
T37	0	12	0	0
T38	0	19	0	0
T39	0	16	0	0