Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1216539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1190745

1

T1

20

T2

1428

T3

4255

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2110024	1			T2	2538		T3	8138		T4	8008
values[0x0]	148172	1			T1	17		T2	156		T3	284
values[0x1]	149088	1			T1	20		T2	169		T3	239

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	973902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1433382

1

T1

24

T2

1751

T3

5108

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7244	1			T2	8		T4	20		T5	32
valid_sources[0x01]	7435	1			T2	11		T3	1		T4	31
valid_sources[0x02]	6729	1			T2	5		T4	21		T5	17
valid_sources[0x03]	11687	1			T2	15		T4	25		T5	15
valid_sources[0x04]	20016	1			T2	9		T4	39		T5	16
valid_sources[0x05]	8366	1			T2	18		T4	14		T5	9
valid_sources[0x06]	11837	1			T2	9		T4	35		T5	13
valid_sources[0x07]	6804	1			T2	4		T4	30		T5	24
valid_sources[0x08]	12037	1			T2	8		T4	36		T5	17
valid_sources[0x09]	13331	1			T2	8		T4	27		T5	14
valid_sources[0x0a]	7015	1			T2	20		T4	21		T5	15
valid_sources[0x0b]	7602	1			T2	8		T4	32		T5	18
valid_sources[0x0c]	19831	1			T2	21		T4	28		T5	19
valid_sources[0x0d]	7187	1			T2	20		T4	21		T5	18
valid_sources[0x0e]	7897	1			T2	6		T4	52		T5	20
valid_sources[0x0f]	7449	1			T2	12		T4	14		T5	12
valid_sources[0x10]	16160	1			T2	8		T4	28		T5	25
valid_sources[0x11]	11265	1			T2	14		T4	22		T5	4
valid_sources[0x12]	11039	1			T2	14		T4	10		T5	13
valid_sources[0x13]	6851	1			T2	6		T4	33		T5	17
valid_sources[0x14]	11778	1			T2	10		T4	48		T5	24
valid_sources[0x15]	7127	1			T2	5		T4	10		T5	13
valid_sources[0x16]	13893	1			T2	12		T4	22		T5	15
valid_sources[0x17]	7418	1			T2	10		T4	44		T5	19
valid_sources[0x18]	8911	1			T2	7		T4	1		T5	12
valid_sources[0x19]	11400	1			T2	15		T4	26		T5	12
valid_sources[0x1a]	6932	1			T2	15		T4	19		T5	8
valid_sources[0x1b]	7554	1			T2	16		T4	46		T5	23
valid_sources[0x1c]	6876	1			T2	13		T4	45		T5	20
valid_sources[0x1d]	11642	1			T2	17		T4	79		T5	16
valid_sources[0x1e]	11918	1			T2	11		T4	52		T5	22
valid_sources[0x1f]	7974	1			T2	17		T4	56		T5	19
valid_sources[0x20]	12156	1			T2	6		T4	69		T5	24
valid_sources[0x21]	12703	1			T2	18		T4	12		T5	16
valid_sources[0x22]	7182	1			T2	10		T4	13		T5	17
valid_sources[0x23]	7119	1			T2	14		T4	11		T5	15
valid_sources[0x24]	6672	1			T2	12		T4	34		T5	14
valid_sources[0x25]	12920	1			T2	12		T4	28		T5	21
valid_sources[0x26]	14572	1			T2	15		T4	25		T5	12
valid_sources[0x27]	7019	1			T2	9		T4	57		T5	13
valid_sources[0x28]	15547	1			T2	11		T4	32		T5	12
valid_sources[0x29]	7140	1			T2	9		T4	4		T5	12
valid_sources[0x2a]	7164	1			T2	12		T4	42		T5	15
valid_sources[0x2b]	6954	1			T2	12		T4	30		T5	19
valid_sources[0x2c]	21190	1			T2	22		T4	46		T5	18
valid_sources[0x2d]	8238	1			T2	18		T4	56		T5	18
valid_sources[0x2e]	15654	1			T2	15		T4	51		T5	19
valid_sources[0x2f]	7048	1			T2	14		T4	21		T5	13
valid_sources[0x30]	8532	1			T2	17		T4	48		T5	17
valid_sources[0x31]	6839	1			T2	8		T4	33		T5	18
valid_sources[0x32]	6849	1			T2	9		T4	36		T5	21
valid_sources[0x33]	7141	1			T2	8		T4	23		T5	17
valid_sources[0x34]	7393	1			T2	11		T4	10		T5	19
valid_sources[0x35]	7872	1			T2	13		T4	21		T5	15
valid_sources[0x36]	7496	1			T2	15		T4	13		T5	16
valid_sources[0x37]	6866	1			T2	7		T4	29		T5	17
valid_sources[0x38]	16089	1			T2	4		T4	39		T5	22
valid_sources[0x39]	12993	1			T2	6		T4	10		T5	23
valid_sources[0x3a]	11925	1			T2	4		T4	17		T5	18
valid_sources[0x3b]	16170	1			T2	19		T4	31		T5	20
valid_sources[0x3c]	12942	1			T2	11		T4	13		T5	26
valid_sources[0x3d]	8053	1			T2	17		T4	33		T5	17
valid_sources[0x3e]	6774	1			T2	21		T4	41		T5	22
valid_sources[0x3f]	6959	1			T2	11		T4	46		T5	12
valid_sources[0x40]	7049	1			T2	9		T4	48		T5	14
valid_sources[0x41]	6950	1			T2	17		T4	72		T5	13
valid_sources[0x42]	8035	1			T2	10		T4	26		T5	21
valid_sources[0x43]	7911	1			T2	8		T4	33		T5	10
valid_sources[0x44]	6873	1			T2	5		T4	19		T5	23
valid_sources[0x45]	7370	1			T2	8		T4	13		T5	21
valid_sources[0x46]	13561	1			T2	10		T4	16		T5	15
valid_sources[0x47]	6904	1			T2	6		T4	42		T5	12
valid_sources[0x48]	8322	1			T2	11		T4	48		T5	17
valid_sources[0x49]	12746	1			T2	9		T4	78		T5	19
valid_sources[0x4a]	7288	1			T2	14		T4	70		T5	13
valid_sources[0x4b]	11568	1			T2	13		T4	52		T5	18
valid_sources[0x4c]	16662	1			T2	14		T3	4322		T4	38
valid_sources[0x4d]	9322	1			T2	4		T4	28		T5	15
valid_sources[0x4e]	7187	1			T2	5		T4	23		T5	19
valid_sources[0x4f]	7613	1			T2	6		T4	43		T5	21
valid_sources[0x50]	9867	1			T2	12		T4	31		T5	13
valid_sources[0x51]	20929	1			T2	6		T4	28		T5	19
valid_sources[0x52]	9477	1			T2	13		T4	46		T5	19
valid_sources[0x53]	24832	1			T2	10		T4	8		T5	22
valid_sources[0x54]	7414	1			T2	10		T4	32		T5	19
valid_sources[0x55]	6918	1			T2	11		T4	21		T5	19
valid_sources[0x56]	7121	1			T2	11		T4	21		T5	20
valid_sources[0x57]	15182	1			T2	7		T4	47		T5	16
valid_sources[0x58]	8113	1			T2	6		T4	26		T5	16
valid_sources[0x59]	12351	1			T2	11		T4	50		T5	10
valid_sources[0x5a]	7234	1			T2	6		T4	21		T5	18
valid_sources[0x5b]	6968	1			T2	14		T4	23		T5	17
valid_sources[0x5c]	6895	1			T2	7		T4	24		T5	20
valid_sources[0x5d]	7728	1			T2	9		T4	72		T5	19
valid_sources[0x5e]	8323	1			T2	6		T4	27		T5	14
valid_sources[0x5f]	11372	1			T2	10		T4	80		T5	20
valid_sources[0x60]	12055	1			T2	13		T4	22		T5	11
valid_sources[0x61]	6994	1			T2	17		T4	40		T5	17
valid_sources[0x62]	7234	1			T2	11		T4	25		T5	13
valid_sources[0x63]	11773	1			T2	10		T4	24		T5	8
valid_sources[0x64]	7934	1			T2	4		T4	13		T5	15
valid_sources[0x65]	7272	1			T2	6		T4	35		T5	18
valid_sources[0x66]	7988	1			T2	15		T4	26		T5	13
valid_sources[0x67]	7041	1			T2	12		T4	28		T5	20
valid_sources[0x68]	11383	1			T2	17		T4	15		T5	22
valid_sources[0x69]	6818	1			T2	12		T4	24		T5	22
valid_sources[0x6a]	14029	1			T2	5		T4	20		T5	21
valid_sources[0x6b]	14640	1			T2	19		T4	9		T5	17
valid_sources[0x6c]	7505	1			T2	20		T4	45		T5	11
valid_sources[0x6d]	8146	1			T2	6		T4	32		T5	15
valid_sources[0x6e]	8489	1			T2	8		T4	39		T5	21
valid_sources[0x6f]	9759	1			T2	16		T4	51		T5	9
valid_sources[0x70]	8053	1			T2	11		T4	45		T5	23
valid_sources[0x71]	7441	1			T2	11		T4	31		T5	20
valid_sources[0x72]	7258	1			T2	9		T4	39		T5	12
valid_sources[0x73]	11262	1			T2	7		T4	35		T5	16
valid_sources[0x74]	7176	1			T2	7		T4	26		T5	24
valid_sources[0x75]	7368	1			T2	7		T4	10		T5	21
valid_sources[0x76]	6919	1			T2	14		T4	29		T5	13
valid_sources[0x77]	6671	1			T2	4		T4	43		T5	12
valid_sources[0x78]	7893	1			T2	8		T4	36		T5	15
valid_sources[0x79]	12570	1			T2	14		T4	37		T5	15
valid_sources[0x7a]	9583	1			T2	12		T4	30		T5	17
valid_sources[0x7b]	7263	1			T2	21		T4	33		T5	12
valid_sources[0x7c]	8899	1			T2	13		T4	56		T5	23
valid_sources[0x7d]	7272	1			T2	14		T4	52		T5	22
valid_sources[0x7e]	6926	1			T2	19		T4	21		T5	14
valid_sources[0x7f]	7639	1			T2	8		T4	37		T5	17
valid_sources[0x80]	20153	1			T2	23		T4	41		T5	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1050618

1

T2

1266

T3

4058

T4

3965

values[0x0]

all_enables

biggest_size

81191

1

T1

11

T2

89

T3

124

values[0x1]

all_enables

biggest_size

58936

1

T1

9

T2

73

T3

73