Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28764	1			T2	24		T3	16		T4	14
auto[PWRUP]	103	1			T54	1		T35	2		T45	2
auto[ONEST_0]	78	1			T54	2		T35	2		T45	1
auto[ONEST_021]	15	1			T59	1		T57	1		T215	1
auto[ONEST_1]	76	1			T54	2		T35	2		T57	3
auto[ONEST_DONE]	11	1			T54	1		T216	1		T217	1
auto[LP_0]	115	1			T35	3		T53	1		T59	1
auto[LP_021]	29	1			T54	1		T55	1		T218	1
auto[LP_1]	125	1			T35	1		T45	1		T53	1
auto[LP_EVAL]	72	1			T59	2		T46	1		T131	1
auto[LP_SLP]	485	1			T54	8		T35	4		T45	4
auto[LP_PWRUP]	28	1			T35	1		T57	1		T55	1
auto[NP_0]	139	1			T54	3		T35	4		T45	1
auto[NP_021]	41	1			T54	2		T53	1		T168	1
auto[NP_1]	163	1			T35	2		T45	1		T53	2
auto[NP_EVAL]	27	1			T35	2		T131	1		T168	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

14

1

T54

1

T35

1

T219

1

min

28266

1

T2

24

T3

16

T4

14

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28282	1			T2	24		T3	16		T4	14
pow[0x1]	7	1			T220	1		T221	1		T222	1
pow[0x2]	15	1			T54	1		T53	1		T57	1
pow[0x3]	37	1			T54	1		T59	1		T57	1
pow[0x4]	72	1			T54	1		T35	1		T45	1
pow[0x5]	118	1			T54	1		T35	1		T45	1
pow[0x6]	268	1			T54	1		T35	6		T45	2
pow[0x7]	506	1			T54	9		T35	11		T45	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

222

1

T54

8

T35

5

T45

2

min

27798

1

T2

24

T3

16

T4

14

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27798	1			T2	24		T3	16		T4	14
pow[0x5]	2	1			T35	1		T223	1		-	-
pow[0x6]	1	1			T224	1		-	-		-	-
pow[0x7]	2	1			T58	1		T225	1		-	-
pow[0x8]	6	1			T220	1		T215	2		T226	1
pow[0x9]	8	1			T173	1		T216	1		T67	1
pow[0xa]	18	1			T227	1		T228	1		T215	1
pow[0xb]	39	1			T54	1		T35	2		T131	2
pow[0xc]	49	1			T53	1		T59	1		T57	1
pow[0xd]	121	1			T54	1		T35	2		T45	1
pow[0xe]	280	1			T54	2		T35	7		T45	4
pow[0xf]	556	1			T54	8		T35	10		T53	8