Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2177	1			T54	15		T34	7		T35	11
auto[PWRUP]	151	1			T54	1		T35	1		T45	2
auto[ONEST_0]	83	1			T54	1		T34	1		T35	3
auto[ONEST_021]	13	1			T60	1		T228	1		T215	1
auto[ONEST_1]	76	1			T45	1		T53	3		T59	3
auto[ONEST_DONE]	4	1			T218	1		T205	1		T354	2
auto[LP_0]	117	1			T54	2		T35	4		T45	2
auto[LP_021]	36	1			T45	1		T55	1		T220	1
auto[LP_1]	154	1			T35	2		T53	1		T59	2
auto[LP_EVAL]	61	1			T34	1		T53	1		T57	2
auto[LP_SLP]	537	1			T54	4		T35	6		T45	8
auto[LP_PWRUP]	33	1			T53	1		T131	1		T220	1
auto[NP_0]	229	1			T54	2		T35	2		T45	3
auto[NP_021]	46	1			T54	1		T45	1		T53	2
auto[NP_1]	257	1			T54	2		T35	1		T45	1
auto[NP_EVAL]	32	1			T45	1		T58	1		T18	1
auto[NP_DONE]	1	1			T173	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T59

1

T168

1

T18

1

min

1938

1

T54

4

T34

8

T35

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1950	1			T54	4		T34	8		T35	7
pow[0x1]	15	1			T60	1		T173	1		T333	2
pow[0x2]	22	1			T53	1		T47	1		T220	1
pow[0x3]	34	1			T35	2		T53	1		T59	2
pow[0x4]	72	1			T53	2		T168	3		T58	1
pow[0x5]	129	1			T54	2		T59	2		T57	4
pow[0x6]	248	1			T54	1		T34	1		T35	2
pow[0x7]	493	1			T54	7		T35	6		T45	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T54

4

T45

1

T53

6

min

1369

1

T54

3

T34

8

T45

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1373	1			T54	3		T34	8		T45	16
pow[0x1]	16	1			T45	3		T15	3		T18	3
pow[0x2]	26	1			T48	2		T49	1		T256	1
pow[0x3]	33	1			T46	2		T16	1		T229	3
pow[0x4]	52	1			T46	1		T47	2		T48	3
pow[0x5]	1	1			T242	1		-	-		-	-
pow[0x7]	3	1			T60	1		T219	1		T225	1
pow[0x8]	4	1			T355	1		T356	1		T357	1
pow[0x9]	11	1			T48	1		T49	1		T358	1
pow[0xa]	20	1			T35	1		T59	1		T227	1
pow[0xb]	37	1			T59	2		T220	1		T228	1
pow[0xc]	71	1			T45	1		T57	2		T131	1
pow[0xd]	130	1			T54	2		T35	2		T45	1
pow[0xe]	320	1			T54	3		T35	4		T45	3
pow[0xf]	557	1			T54	8		T34	1		T35	10