Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	32209942	32127662	0	0
FsmStateHwReset_A	1199	1199	0	0
FsmStateSwReset_A	32209942	6662	0	0
LpSampleCntHwReset_A	1199	1199	0	0
LpSampleCntSwReset_A	32209942	6662	0	0
NpSampleCntHwReset_A	1199	1199	0	0
NpSampleCntSwReset_A	32209942	6662	0	0
PwrupTimerCntHwReset_A	1199	1199	0	0
PwrupTimerCntSwReset_A	32209942	6662	0	0
WakeupTimerCntHwReset_A	1199	1199	0	0
WakeupTimerCntSwReset_A	32209942	6662	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32209942	32127662	0	0
T1	659	602	0	0
T2	99348	99257	0	0
T3	66054	65980	0	0
T4	64685	64624	0	0
T5	33156	33059	0	0
T6	65271	65211	0	0
T7	577	483	0	0
T8	36652	36574	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199	1199	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32209942	6662	0	0
T2	99348	24	0	0
T3	66054	16	0	0
T4	64685	14	0	0
T5	33156	6	0	0
T6	65271	17	0	0
T7	577	0	0	0
T8	36652	8	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	17	0	0
T12	0	24	0	0
T13	0	12	0	0
T14	0	7	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199	1199	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32209942	6662	0	0
T2	99348	24	0	0
T3	66054	16	0	0
T4	64685	14	0	0
T5	33156	6	0	0
T6	65271	17	0	0
T7	577	0	0	0
T8	36652	8	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	17	0	0
T12	0	24	0	0
T13	0	12	0	0
T14	0	7	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199	1199	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32209942	6662	0	0
T2	99348	24	0	0
T3	66054	16	0	0
T4	64685	14	0	0
T5	33156	6	0	0
T6	65271	17	0	0
T7	577	0	0	0
T8	36652	8	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	17	0	0
T12	0	24	0	0
T13	0	12	0	0
T14	0	7	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199	1199	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32209942	6662	0	0
T2	99348	24	0	0
T3	66054	16	0	0
T4	64685	14	0	0
T5	33156	6	0	0
T6	65271	17	0	0
T7	577	0	0	0
T8	36652	8	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	17	0	0
T12	0	24	0	0
T13	0	12	0	0
T14	0	7	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199	1199	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32209942	6662	0	0
T2	99348	24	0	0
T3	66054	16	0	0
T4	64685	14	0	0
T5	33156	6	0	0
T6	65271	17	0	0
T7	577	0	0	0
T8	36652	8	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	17	0	0
T12	0	24	0	0
T13	0	12	0	0
T14	0	7	0	0