Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2490	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2376	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2236	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2675	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2606	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2545	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2524	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2505	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2557	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2404	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2673	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2614	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2257	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2592	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2481	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2564	0	0
adc_en_ctl_rd_A	2147483647	2125	0	0
adc_fsm_rst_rd_A	2147483647	2008	0	0
adc_intr_ctl_rd_A	2147483647	2548	0	0
adc_lp_sample_ctl_rd_A	2147483647	2053	0	0
adc_pd_ctl_rd_A	2147483647	2256	0	0
adc_sample_ctl_rd_A	2147483647	1940	0	0
adc_wakeup_ctl_rd_A	2147483647	2252	0	0
intr_enable_rd_A	2147483647	2811	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2490	0	0
T15	187631	10	0	0
T16	0	27	0	0
T17	0	48	0	0
T18	0	19	0	0
T19	0	32	0	0
T20	0	18	0	0
T21	0	17	0	0
T22	0	14	0	0
T23	0	19	0	0
T24	0	13	0	0
T25	163586	0	0	0
T26	44240	0	0	0
T27	227810	0	0	0
T28	145943	0	0	0
T29	322920	0	0	0
T30	769420	0	0	0
T31	637214	0	0	0
T32	323219	0	0	0
T33	178738	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2376	0	0
T15	0	13	0	0
T16	0	20	0	0
T17	0	42	0	0
T18	0	26	0	0
T19	0	36	0	0
T20	0	43	0	0
T21	0	18	0	0
T22	0	17	0	0
T23	0	9	0	0
T34	446051	6	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2236	0	0
T15	187631	5	0	0
T16	0	17	0	0
T17	0	17	0	0
T18	0	14	0	0
T19	0	38	0	0
T20	0	13	0	0
T21	0	22	0	0
T22	0	14	0	0
T23	0	18	0	0
T24	0	6	0	0
T25	163586	0	0	0
T26	44240	0	0	0
T27	227810	0	0	0
T28	145943	0	0	0
T29	322920	0	0	0
T30	769420	0	0	0
T31	637214	0	0	0
T32	323219	0	0	0
T33	178738	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2675	0	0
T15	0	6	0	0
T16	0	33	0	0
T17	0	26	0	0
T18	0	16	0	0
T19	0	39	0	0
T20	0	16	0	0
T21	0	20	0	0
T22	0	28	0	0
T23	0	21	0	0
T34	446051	3	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2606	0	0
T15	0	15	0	0
T16	0	18	0	0
T17	0	29	0	0
T18	0	18	0	0
T19	0	38	0	0
T20	0	26	0	0
T21	0	30	0	0
T22	0	29	0	0
T23	0	9	0	0
T34	446051	13	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2545	0	0
T15	0	8	0	0
T16	0	18	0	0
T17	0	39	0	0
T18	0	10	0	0
T19	0	38	0	0
T20	0	19	0	0
T21	0	14	0	0
T22	0	18	0	0
T23	0	11	0	0
T34	446051	14	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2524	0	0
T15	0	7	0	0
T16	0	30	0	0
T17	0	28	0	0
T18	0	20	0	0
T19	0	48	0	0
T20	0	34	0	0
T21	0	10	0	0
T22	0	27	0	0
T23	0	13	0	0
T34	446051	4	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2505	0	0
T16	0	11	0	0
T17	0	43	0	0
T18	0	20	0	0
T19	0	32	0	0
T20	0	5	0	0
T21	0	30	0	0
T22	0	26	0	0
T23	0	4	0	0
T24	0	12	0	0
T34	446051	14	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2557	0	0
T15	0	8	0	0
T16	0	25	0	0
T17	0	29	0	0
T18	0	20	0	0
T19	0	26	0	0
T20	0	31	0	0
T21	0	31	0	0
T22	0	19	0	0
T23	0	20	0	0
T34	446051	13	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T15	0	14	0	0
T16	0	23	0	0
T17	0	20	0	0
T18	0	23	0	0
T19	0	40	0	0
T20	0	12	0	0
T21	0	16	0	0
T22	0	19	0	0
T23	0	14	0	0
T34	446051	5	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2673	0	0
T15	0	21	0	0
T16	0	25	0	0
T17	0	13	0	0
T18	0	26	0	0
T19	0	34	0	0
T20	0	9	0	0
T21	0	21	0	0
T22	0	28	0	0
T23	0	19	0	0
T34	446051	12	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2614	0	0
T15	0	18	0	0
T16	0	33	0	0
T17	0	34	0	0
T18	0	19	0	0
T19	0	35	0	0
T20	0	19	0	0
T21	0	19	0	0
T22	0	26	0	0
T23	0	33	0	0
T34	446051	14	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2257	0	0
T15	0	15	0	0
T16	0	13	0	0
T17	0	47	0	0
T18	0	27	0	0
T19	0	33	0	0
T20	0	14	0	0
T21	0	14	0	0
T22	0	15	0	0
T23	0	13	0	0
T34	446051	7	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2592	0	0
T15	0	15	0	0
T16	0	20	0	0
T17	0	47	0	0
T18	0	18	0	0
T19	0	34	0	0
T20	0	37	0	0
T21	0	14	0	0
T22	0	16	0	0
T23	0	12	0	0
T34	446051	4	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2481	0	0
T15	0	4	0	0
T16	0	31	0	0
T17	0	38	0	0
T18	0	19	0	0
T19	0	39	0	0
T20	0	25	0	0
T21	0	21	0	0
T22	0	22	0	0
T23	0	11	0	0
T34	446051	14	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2564	0	0
T15	0	11	0	0
T16	0	13	0	0
T17	0	38	0	0
T18	0	27	0	0
T19	0	32	0	0
T20	0	22	0	0
T21	0	13	0	0
T22	0	20	0	0
T23	0	17	0	0
T34	446051	4	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2125	0	0
T15	0	12	0	0
T16	0	21	0	0
T17	0	38	0	0
T18	0	22	0	0
T19	0	44	0	0
T20	0	25	0	0
T21	0	25	0	0
T22	0	20	0	0
T23	0	10	0	0
T34	446051	17	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T15	187631	5	0	0
T16	0	27	0	0
T17	0	41	0	0
T18	0	15	0	0
T19	0	14	0	0
T20	0	22	0	0
T21	0	19	0	0
T22	0	14	0	0
T23	0	18	0	0
T24	0	31	0	0
T25	163586	0	0	0
T26	44240	0	0	0
T27	227810	0	0	0
T28	145943	0	0	0
T29	322920	0	0	0
T30	769420	0	0	0
T31	637214	0	0	0
T32	323219	0	0	0
T33	178738	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2548	0	0
T15	0	13	0	0
T16	0	8	0	0
T17	0	32	0	0
T18	0	27	0	0
T19	0	22	0	0
T20	0	8	0	0
T21	0	23	0	0
T22	0	25	0	0
T23	0	13	0	0
T34	446051	7	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2053	0	0
T15	0	9	0	0
T16	0	10	0	0
T17	0	13	0	0
T18	0	22	0	0
T19	0	32	0	0
T20	0	18	0	0
T21	0	28	0	0
T22	0	24	0	0
T23	0	8	0	0
T34	446051	11	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T15	0	10	0	0
T16	0	15	0	0
T17	0	22	0	0
T18	0	18	0	0
T19	0	57	0	0
T20	0	38	0	0
T21	0	19	0	0
T22	0	19	0	0
T23	0	18	0	0
T34	446051	6	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T15	0	6	0	0
T16	0	25	0	0
T17	0	40	0	0
T18	0	20	0	0
T19	0	42	0	0
T20	0	15	0	0
T21	0	29	0	0
T22	0	16	0	0
T23	0	15	0	0
T34	446051	22	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2252	0	0
T15	0	3	0	0
T16	0	21	0	0
T17	0	48	0	0
T18	0	15	0	0
T19	0	27	0	0
T20	0	13	0	0
T21	0	21	0	0
T22	0	23	0	0
T23	0	12	0	0
T34	446051	10	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2811	0	0
T15	0	5	0	0
T16	0	35	0	0
T17	0	58	0	0
T18	0	44	0	0
T19	0	30	0	0
T20	0	49	0	0
T21	0	4	0	0
T22	0	32	0	0
T34	446051	27	0	0
T35	105811	0	0	0
T36	345418	0	0	0
T37	569355	0	0	0
T38	16022	0	0	0
T39	573466	0	0	0
T40	990484	0	0	0
T41	241213	0	0	0
T42	874471	0	0	0
T43	994795	0	0	0
T44	0	5	0	0