Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1206447	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1177003

1

T1

248

T2

2041

T3

942

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2080341	1			T1	240		T2	3979		T3	1698
values[0x0]	150795	1			T1	111		T2	134		T3	99
values[0x1]	152314	1			T1	93		T2	117		T3	104

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	966328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1417122

1

T1

290

T2

2493

T3

1135

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8444	1			T2	11		T3	2		T4	2
valid_sources[0x01]	12051	1			T2	16		T3	9		T4	7
valid_sources[0x02]	6986	1			T2	22		T3	7		T4	1
valid_sources[0x03]	19914	1			T2	19		T3	9		T4	6
valid_sources[0x04]	9727	1			T2	12		T3	7		T4	5
valid_sources[0x05]	7119	1			T2	10		T3	7		T4	6
valid_sources[0x06]	6861	1			T2	17		T3	5		T4	6
valid_sources[0x07]	11757	1			T2	11		T3	9		T4	5
valid_sources[0x08]	6731	1			T2	21		T3	9		T4	6
valid_sources[0x09]	6429	1			T2	19		T3	7		T4	3
valid_sources[0x0a]	7092	1			T2	11		T3	13		T4	7
valid_sources[0x0b]	9495	1			T2	10		T3	6		T4	1
valid_sources[0x0c]	8264	1			T2	16		T3	10		T4	10
valid_sources[0x0d]	12844	1			T2	2		T3	3		T4	3
valid_sources[0x0e]	7664	1			T1	1		T2	17		T3	10
valid_sources[0x0f]	6786	1			T2	18		T3	8		T4	1
valid_sources[0x10]	11116	1			T1	1		T2	22		T3	18
valid_sources[0x11]	11320	1			T2	11		T3	5		T4	5
valid_sources[0x12]	6839	1			T1	2		T2	16		T3	1
valid_sources[0x13]	11896	1			T1	2		T2	13		T3	10
valid_sources[0x14]	6488	1			T2	15		T3	4		T4	5
valid_sources[0x15]	8172	1			T1	1		T2	25		T3	4
valid_sources[0x16]	7886	1			T2	23		T3	9		T4	6
valid_sources[0x17]	9392	1			T2	14		T3	9		T4	4
valid_sources[0x18]	11132	1			T2	15		T3	10		T4	6
valid_sources[0x19]	7778	1			T2	12		T3	11		T4	8
valid_sources[0x1a]	6656	1			T2	10		T3	8		T4	3
valid_sources[0x1b]	10997	1			T1	2		T2	16		T3	10
valid_sources[0x1c]	10643	1			T1	2		T2	15		T3	7
valid_sources[0x1d]	15530	1			T1	1		T2	28		T3	7
valid_sources[0x1e]	8010	1			T2	19		T3	3		T4	10
valid_sources[0x1f]	8182	1			T1	1		T2	17		T3	6
valid_sources[0x20]	12039	1			T2	6		T3	11		T4	7
valid_sources[0x21]	14914	1			T1	3		T2	12		T3	9
valid_sources[0x22]	10192	1			T1	2		T2	26		T3	8
valid_sources[0x23]	9743	1			T1	5		T2	9		T3	4
valid_sources[0x24]	6476	1			T2	18		T3	2		T4	1
valid_sources[0x25]	6708	1			T1	1		T2	15		T3	15
valid_sources[0x26]	11562	1			T2	25		T3	4		T4	4
valid_sources[0x27]	7306	1			T2	18		T3	7		T4	3
valid_sources[0x28]	19379	1			T1	1		T2	18		T3	5
valid_sources[0x29]	7592	1			T1	11		T2	12		T3	8
valid_sources[0x2a]	11787	1			T2	13		T3	10		T6	3
valid_sources[0x2b]	23353	1			T2	13		T3	7		T4	4
valid_sources[0x2c]	9576	1			T1	2		T2	6		T3	11
valid_sources[0x2d]	28635	1			T1	2		T2	12		T3	10
valid_sources[0x2e]	7689	1			T1	1		T2	13		T3	6
valid_sources[0x2f]	7953	1			T2	17		T3	4		T4	10
valid_sources[0x30]	16299	1			T2	21		T3	20		T4	5
valid_sources[0x31]	6521	1			T2	19		T3	6		T4	4
valid_sources[0x32]	15415	1			T1	2		T2	21		T3	9
valid_sources[0x33]	6857	1			T2	18		T3	7		T4	3
valid_sources[0x34]	13173	1			T2	14		T3	11		T4	2
valid_sources[0x35]	15209	1			T2	21		T3	9		T4	9
valid_sources[0x36]	25949	1			T2	23		T3	13		T4	3
valid_sources[0x37]	7807	1			T2	24		T3	7		T4	1
valid_sources[0x38]	6954	1			T1	4		T2	18		T3	6
valid_sources[0x39]	6567	1			T2	13		T3	7		T4	9
valid_sources[0x3a]	12131	1			T1	1		T2	16		T3	11
valid_sources[0x3b]	11718	1			T1	4		T2	5		T3	5
valid_sources[0x3c]	7215	1			T2	23		T3	8		T4	2
valid_sources[0x3d]	7874	1			T2	10		T3	15		T4	2
valid_sources[0x3e]	7162	1			T2	11		T3	3		T4	4
valid_sources[0x3f]	13337	1			T2	23		T3	6		T4	3
valid_sources[0x40]	6961	1			T1	1		T2	12		T3	8
valid_sources[0x41]	6378	1			T1	2		T2	19		T3	10
valid_sources[0x42]	6736	1			T2	16		T3	7		T4	6
valid_sources[0x43]	9659	1			T1	2		T2	21		T3	11
valid_sources[0x44]	8875	1			T2	15		T3	8		T4	7
valid_sources[0x45]	6930	1			T1	1		T2	21		T3	13
valid_sources[0x46]	7810	1			T1	1		T2	21		T3	14
valid_sources[0x47]	6773	1			T2	14		T3	7		T4	5
valid_sources[0x48]	7076	1			T1	2		T2	20		T3	8
valid_sources[0x49]	6925	1			T2	27		T3	11		T4	6
valid_sources[0x4a]	6679	1			T2	16		T3	11		T4	5
valid_sources[0x4b]	6627	1			T1	2		T2	14		T3	8
valid_sources[0x4c]	18530	1			T2	5		T3	10		T4	2
valid_sources[0x4d]	9762	1			T2	30		T3	13		T4	2
valid_sources[0x4e]	9986	1			T2	13		T3	6		T4	6
valid_sources[0x4f]	7172	1			T1	1		T2	10		T3	8
valid_sources[0x50]	12153	1			T1	15		T2	17		T4	8
valid_sources[0x51]	8680	1			T2	7		T3	6		T4	5
valid_sources[0x52]	7615	1			T1	1		T2	21		T3	5
valid_sources[0x53]	7109	1			T1	3		T2	22		T3	4
valid_sources[0x54]	19479	1			T2	32		T3	9		T4	2
valid_sources[0x55]	8773	1			T1	1		T2	21		T3	6
valid_sources[0x56]	11351	1			T1	1		T2	8		T3	10
valid_sources[0x57]	7435	1			T2	23		T3	7		T4	6
valid_sources[0x58]	6675	1			T2	29		T3	6		T4	2
valid_sources[0x59]	6896	1			T2	17		T3	3		T4	6
valid_sources[0x5a]	11842	1			T2	18		T3	3		T4	2
valid_sources[0x5b]	6650	1			T2	18		T3	7		T4	2
valid_sources[0x5c]	6865	1			T1	5		T2	26		T3	9
valid_sources[0x5d]	8507	1			T1	2		T2	14		T3	9
valid_sources[0x5e]	6646	1			T1	1		T2	14		T3	9
valid_sources[0x5f]	6961	1			T2	22		T3	8		T4	13
valid_sources[0x60]	6659	1			T1	3		T2	17		T3	5
valid_sources[0x61]	6619	1			T2	31		T3	7		T4	6
valid_sources[0x62]	6669	1			T2	20		T3	11		T4	8
valid_sources[0x63]	9222	1			T2	16		T3	2		T4	6
valid_sources[0x64]	6684	1			T1	1		T2	26		T3	5
valid_sources[0x65]	7755	1			T1	1		T2	22		T3	5
valid_sources[0x66]	6565	1			T1	1		T2	19		T3	5
valid_sources[0x67]	7370	1			T2	16		T3	13		T4	4
valid_sources[0x68]	6360	1			T1	1		T2	11		T3	9
valid_sources[0x69]	7028	1			T2	18		T3	8		T4	5
valid_sources[0x6a]	6547	1			T2	7		T3	3		T4	6
valid_sources[0x6b]	6739	1			T2	20		T3	8		T4	4
valid_sources[0x6c]	15983	1			T1	1		T2	26		T3	3
valid_sources[0x6d]	8884	1			T1	3		T2	19		T3	4
valid_sources[0x6e]	6985	1			T1	127		T2	15		T3	6
valid_sources[0x6f]	11404	1			T2	10		T3	5		T4	7
valid_sources[0x70]	7866	1			T2	24		T3	6		T4	3
valid_sources[0x71]	7642	1			T2	12		T3	6		T4	4
valid_sources[0x72]	7038	1			T2	21		T3	6		T4	9
valid_sources[0x73]	11042	1			T2	21		T3	9		T4	3
valid_sources[0x74]	6705	1			T1	1		T2	15		T3	11
valid_sources[0x75]	7154	1			T2	4		T3	8		T4	4
valid_sources[0x76]	6914	1			T2	21		T3	4		T4	9
valid_sources[0x77]	7023	1			T1	1		T2	22		T3	8
valid_sources[0x78]	7226	1			T2	13		T3	11		T4	6
valid_sources[0x79]	10840	1			T1	1		T2	25		T3	7
valid_sources[0x7a]	7614	1			T1	2		T2	25		T3	11
valid_sources[0x7b]	19569	1			T2	14		T3	3		T4	2
valid_sources[0x7c]	6450	1			T2	12		T3	7		T4	5
valid_sources[0x7d]	9617	1			T2	26		T3	7		T4	4
valid_sources[0x7e]	6765	1			T1	4		T2	17		T3	11
valid_sources[0x7f]	6935	1			T2	13		T3	4		T4	3
valid_sources[0x80]	7687	1			T2	18		T3	11		T8	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1036094

1

T1

131

T2

1949

T3

839

values[0x0]

all_enables

biggest_size

81613

1

T1

72

T2

62

T3

61

values[0x1]

all_enables

biggest_size

59296

1

T1

45

T2

30

T3

42