Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31320	1			T2	8		T3	17		T4	235
auto[PWRUP]	120	1			T4	1		T45	3		T44	1
auto[ONEST_0]	71	1			T4	1		T45	1		T44	1
auto[ONEST_021]	17	1			T201	1		T19	1		T202	1
auto[ONEST_1]	76	1			T4	3		T37	1		T44	1
auto[ONEST_DONE]	6	1			T165	1		T19	1		T203	1
auto[LP_0]	162	1			T4	1		T45	2		T44	3
auto[LP_021]	35	1			T37	1		T15	1		T27	1
auto[LP_1]	157	1			T4	3		T45	1		T37	1
auto[LP_EVAL]	73	1			T4	1		T37	1		T204	2
auto[LP_SLP]	523	1			T4	4		T45	7		T37	1
auto[LP_PWRUP]	21	1			T44	1		T205	1		T49	1
auto[NP_0]	189	1			T4	3		T45	2		T37	3
auto[NP_021]	37	1			T44	1		T15	3		T27	1
auto[NP_1]	188	1			T4	1		T45	5		T37	1
auto[NP_EVAL]	54	1			T4	1		T165	2		T15	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T44

1

T16

1

T206

1

min

30728

1

T2

8

T3

17

T4

222

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30738	1			T2	8		T3	17		T4	222
pow[0x1]	4	1			T205	1		T207	1		T208	1
pow[0x2]	17	1			T204	1		T27	1		T206	1
pow[0x3]	33	1			T44	3		T27	1		T205	1
pow[0x4]	77	1			T4	2		T44	1		T38	1
pow[0x5]	136	1			T4	2		T45	2		T37	1
pow[0x6]	302	1			T4	4		T45	6		T37	4
pow[0x7]	598	1			T4	11		T45	7		T37	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

230

1

T4

4

T45

1

T44

4

min

30244

1

T2

8

T3

17

T4

221

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30244	1			T2	8		T3	17		T4	221
pow[0x3]	1	1			T57	1		-	-		-	-
pow[0x5]	3	1			T45	1		T49	1		T208	1
pow[0x6]	1	1			T209	1		-	-		-	-
pow[0x7]	4	1			T210	1		T201	1		T211	1
pow[0x8]	5	1			T212	2		T213	2		T214	1
pow[0x9]	12	1			T19	1		T215	1		T202	1
pow[0xa]	31	1			T44	1		T38	1		T204	3
pow[0xb]	53	1			T4	2		T37	2		T44	2
pow[0xc]	76	1			T45	2		T37	1		T44	1
pow[0xd]	175	1			T4	2		T45	2		T37	2
pow[0xe]	308	1			T4	5		T45	3		T44	7
pow[0xf]	614	1			T4	7		T45	9		T44	8