Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2414	1			T1	9		T4	16		T45	18
auto[PWRUP]	154	1			T4	1		T45	1		T37	3
auto[ONEST_0]	95	1			T204	1		T165	3		T15	2
auto[ONEST_021]	23	1			T4	1		T28	1		T159	1
auto[ONEST_1]	103	1			T45	2		T35	1		T37	1
auto[ONEST_DONE]	3	1			T4	1		T209	1		T208	1
auto[LP_0]	114	1			T4	2		T45	2		T44	1
auto[LP_021]	32	1			T45	1		T15	2		T16	1
auto[LP_1]	131	1			T4	2		T45	1		T38	1
auto[LP_EVAL]	53	1			T36	1		T37	1		T44	1
auto[LP_SLP]	617	1			T4	12		T45	3		T37	6
auto[LP_PWRUP]	30	1			T35	1		T32	2		T205	1
auto[NP_0]	212	1			T1	1		T4	2		T45	4
auto[NP_021]	60	1			T1	1		T45	2		T36	1
auto[NP_1]	227	1			T4	3		T35	2		T36	1
auto[NP_EVAL]	38	1			T204	1		T15	1		T27	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T165

1

T49

1

T340

1

min

2079

1

T1

11

T4

16

T45

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2097	1			T1	11		T4	16		T45	8
pow[0x1]	12	1			T4	1		T38	2		T15	1
pow[0x2]	17	1			T38	1		T341	1		T158	1
pow[0x3]	43	1			T38	1		T204	1		T15	1
pow[0x4]	66	1			T37	1		T38	1		T15	1
pow[0x5]	122	1			T4	2		T45	3		T44	1
pow[0x6]	290	1			T4	4		T45	4		T36	1
pow[0x7]	546	1			T4	4		T45	7		T36	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

198

1

T4

1

T45

4

T44

2

min

1391

1

T1

9

T4

1

T45

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1399	1			T1	9		T4	1		T45	7
pow[0x1]	19	1			T39	1		T253	2		T342	1
pow[0x2]	33	1			T1	1		T38	1		T39	1
pow[0x3]	56	1			T1	1		T37	4		T38	2
pow[0x4]	48	1			T35	2		T36	3		T39	3
pow[0x5]	1	1			T202	1		-	-		-	-
pow[0x6]	2	1			T213	1		T343	1		-	-
pow[0x7]	4	1			T44	1		T344	1		T212	1
pow[0x8]	3	1			T38	1		T345	1		T346	1
pow[0x9]	7	1			T205	1		T49	1		T347	3
pow[0xa]	19	1			T4	1		T158	1		T159	1
pow[0xb]	43	1			T45	2		T204	1		T165	1
pow[0xc]	85	1			T4	1		T44	1		T204	1
pow[0xd]	169	1			T45	1		T37	1		T38	2
pow[0xe]	334	1			T4	3		T45	3		T37	2
pow[0xf]	677	1			T4	11		T45	5		T36	1