Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2173	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2135	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2196	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2123	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2006	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2026	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2304	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2202	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2287	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2040	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2088	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2111	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2021	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2069	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2019	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2095	0	0
adc_en_ctl_rd_A	2147483647	1741	0	0
adc_fsm_rst_rd_A	2147483647	1650	0	0
adc_intr_ctl_rd_A	2147483647	2406	0	0
adc_lp_sample_ctl_rd_A	2147483647	1663	0	0
adc_pd_ctl_rd_A	2147483647	1965	0	0
adc_sample_ctl_rd_A	2147483647	1628	0	0
adc_wakeup_ctl_rd_A	2147483647	1636	0	0
intr_enable_rd_A	2147483647	2603	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2173	0	0
T15	589319	35	0	0
T16	227669	31	0	0
T17	0	27	0	0
T18	0	23	0	0
T19	0	43	0	0
T20	0	44	0	0
T21	0	44	0	0
T22	0	26	0	0
T23	0	23	0	0
T24	0	25	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2135	0	0
T15	589319	32	0	0
T16	227669	17	0	0
T17	0	25	0	0
T18	0	17	0	0
T19	0	42	0	0
T20	0	39	0	0
T21	0	28	0	0
T22	0	33	0	0
T23	0	16	0	0
T24	0	48	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2196	0	0
T15	589319	45	0	0
T16	227669	21	0	0
T17	0	20	0	0
T18	0	24	0	0
T19	0	59	0	0
T20	0	25	0	0
T21	0	48	0	0
T22	0	25	0	0
T23	0	16	0	0
T24	0	36	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2123	0	0
T15	589319	43	0	0
T16	227669	29	0	0
T17	0	18	0	0
T18	0	19	0	0
T19	0	45	0	0
T20	0	33	0	0
T21	0	30	0	0
T22	0	19	0	0
T23	0	16	0	0
T24	0	51	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006	0	0
T15	589319	26	0	0
T16	227669	8	0	0
T17	0	16	0	0
T18	0	5	0	0
T19	0	38	0	0
T20	0	22	0	0
T21	0	38	0	0
T22	0	33	0	0
T23	0	22	0	0
T24	0	41	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2026	0	0
T15	589319	23	0	0
T16	227669	19	0	0
T17	0	19	0	0
T18	0	32	0	0
T19	0	24	0	0
T20	0	42	0	0
T21	0	45	0	0
T22	0	26	0	0
T23	0	17	0	0
T24	0	33	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2304	0	0
T15	589319	40	0	0
T16	227669	26	0	0
T17	0	32	0	0
T18	0	14	0	0
T19	0	38	0	0
T20	0	45	0	0
T21	0	55	0	0
T22	0	35	0	0
T23	0	34	0	0
T24	0	32	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2202	0	0
T15	589319	34	0	0
T16	227669	25	0	0
T17	0	15	0	0
T18	0	12	0	0
T19	0	43	0	0
T20	0	23	0	0
T21	0	38	0	0
T22	0	28	0	0
T23	0	16	0	0
T24	0	18	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T15	589319	47	0	0
T16	227669	19	0	0
T17	0	24	0	0
T18	0	24	0	0
T19	0	36	0	0
T20	0	35	0	0
T21	0	60	0	0
T22	0	33	0	0
T23	0	22	0	0
T24	0	43	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T15	589319	31	0	0
T16	227669	30	0	0
T17	0	14	0	0
T18	0	20	0	0
T19	0	49	0	0
T20	0	37	0	0
T21	0	61	0	0
T22	0	28	0	0
T23	0	10	0	0
T24	0	21	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2088	0	0
T15	589319	36	0	0
T16	227669	9	0	0
T17	0	23	0	0
T18	0	21	0	0
T19	0	28	0	0
T20	0	41	0	0
T21	0	47	0	0
T22	0	37	0	0
T23	0	15	0	0
T24	0	37	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2111	0	0
T15	589319	22	0	0
T16	227669	21	0	0
T17	0	16	0	0
T18	0	31	0	0
T19	0	33	0	0
T20	0	31	0	0
T21	0	32	0	0
T22	0	22	0	0
T23	0	27	0	0
T24	0	48	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2021	0	0
T15	589319	37	0	0
T16	227669	20	0	0
T17	0	17	0	0
T18	0	12	0	0
T19	0	35	0	0
T20	0	31	0	0
T21	0	36	0	0
T22	0	28	0	0
T23	0	9	0	0
T24	0	29	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2069	0	0
T15	589319	33	0	0
T16	227669	20	0	0
T17	0	16	0	0
T18	0	28	0	0
T19	0	26	0	0
T20	0	11	0	0
T21	0	42	0	0
T22	0	35	0	0
T23	0	17	0	0
T24	0	35	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2019	0	0
T15	589319	14	0	0
T16	227669	23	0	0
T17	0	11	0	0
T18	0	19	0	0
T19	0	47	0	0
T20	0	24	0	0
T21	0	45	0	0
T22	0	45	0	0
T23	0	22	0	0
T24	0	37	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T15	589319	45	0	0
T16	227669	10	0	0
T17	0	15	0	0
T18	0	14	0	0
T19	0	45	0	0
T20	0	30	0	0
T21	0	55	0	0
T22	0	32	0	0
T23	0	12	0	0
T24	0	26	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1741	0	0
T15	589319	33	0	0
T16	227669	17	0	0
T17	0	13	0	0
T18	0	27	0	0
T19	0	46	0	0
T20	0	57	0	0
T21	0	29	0	0
T22	0	18	0	0
T23	0	7	0	0
T24	0	37	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1650	0	0
T15	589319	30	0	0
T16	227669	27	0	0
T17	0	22	0	0
T18	0	24	0	0
T19	0	9	0	0
T20	0	38	0	0
T21	0	45	0	0
T22	0	24	0	0
T23	0	24	0	0
T24	0	43	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2406	0	0
T15	589319	47	0	0
T16	227669	34	0	0
T17	0	17	0	0
T18	0	26	0	0
T19	0	37	0	0
T20	0	46	0	0
T21	0	33	0	0
T22	0	25	0	0
T23	0	19	0	0
T24	0	26	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1663	0	0
T15	589319	31	0	0
T16	227669	19	0	0
T17	0	12	0	0
T18	0	17	0	0
T19	0	39	0	0
T20	0	41	0	0
T21	0	51	0	0
T22	0	26	0	0
T23	0	14	0	0
T24	0	34	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1965	0	0
T15	589319	44	0	0
T16	227669	14	0	0
T17	0	12	0	0
T18	0	9	0	0
T19	0	34	0	0
T20	0	29	0	0
T21	0	45	0	0
T22	0	40	0	0
T23	0	6	0	0
T24	0	27	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1628	0	0
T15	589319	26	0	0
T16	227669	19	0	0
T17	0	23	0	0
T18	0	30	0	0
T19	0	41	0	0
T20	0	31	0	0
T21	0	31	0	0
T22	0	29	0	0
T23	0	17	0	0
T24	0	36	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1636	0	0
T15	589319	39	0	0
T16	227669	21	0	0
T17	0	21	0	0
T18	0	13	0	0
T19	0	23	0	0
T20	0	30	0	0
T21	0	58	0	0
T22	0	27	0	0
T23	0	20	0	0
T24	0	49	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2603	0	0
T15	589319	82	0	0
T16	227669	12	0	0
T17	0	52	0	0
T18	0	27	0	0
T19	0	64	0	0
T20	0	34	0	0
T21	0	73	0	0
T22	0	43	0	0
T25	117373	0	0	0
T26	759494	0	0	0
T27	421626	0	0	0
T28	195584	0	0	0
T29	295400	0	0	0
T30	785793	0	0	0
T31	863642	0	0	0
T32	169284	0	0	0
T33	0	26	0	0
T34	0	31	0	0