Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1187725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1158348

1

T1

4286

T2

22

T3

1379

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2037191	1			T1	8263		T3	2543		T4	814
values[0x0]	153708	1			T1	228		T2	30		T3	158
values[0x1]	155174	1			T1	263		T2	16		T3	138

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	951708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1394365

1

T1

5167

T2

26

T3

1702

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7621	1			T1	36		T3	5		T4	2
valid_sources[0x01]	6691	1			T1	35		T3	3		T5	19
valid_sources[0x02]	15289	1			T1	30		T3	5		T4	1
valid_sources[0x03]	6740	1			T1	35		T3	34		T5	23
valid_sources[0x04]	6840	1			T1	22		T3	11		T4	12
valid_sources[0x05]	8304	1			T1	35		T3	5		T5	11
valid_sources[0x06]	7900	1			T1	21		T5	24		T6	2
valid_sources[0x07]	8746	1			T1	36		T3	2		T5	27
valid_sources[0x08]	10365	1			T1	35		T3	4		T5	15
valid_sources[0x09]	6804	1			T1	38		T3	4		T4	5
valid_sources[0x0a]	10047	1			T1	29		T3	5		T4	2
valid_sources[0x0b]	6675	1			T1	29		T3	5		T4	19
valid_sources[0x0c]	6323	1			T1	34		T3	4		T5	17
valid_sources[0x0d]	16422	1			T1	46		T3	17		T4	4
valid_sources[0x0e]	6645	1			T1	33		T3	5		T4	8
valid_sources[0x0f]	14955	1			T1	38		T3	10		T4	9
valid_sources[0x10]	9288	1			T1	43		T3	7		T4	1
valid_sources[0x11]	6684	1			T1	38		T3	9		T4	2
valid_sources[0x12]	6614	1			T1	37		T3	4		T5	22
valid_sources[0x13]	7898	1			T1	33		T3	16		T5	21
valid_sources[0x14]	7030	1			T1	22		T3	18		T5	10
valid_sources[0x15]	16619	1			T1	39		T3	3		T4	2
valid_sources[0x16]	6617	1			T1	34		T3	6		T4	9
valid_sources[0x17]	6737	1			T1	31		T3	4		T4	4
valid_sources[0x18]	6936	1			T1	43		T3	11		T4	4
valid_sources[0x19]	6743	1			T1	32		T3	2		T4	10
valid_sources[0x1a]	6466	1			T1	34		T3	24		T5	23
valid_sources[0x1b]	8944	1			T1	29		T3	4		T4	7
valid_sources[0x1c]	11738	1			T1	37		T3	6		T4	4
valid_sources[0x1d]	6529	1			T1	40		T3	6		T4	1
valid_sources[0x1e]	9823	1			T1	34		T3	3		T5	21
valid_sources[0x1f]	6737	1			T1	38		T3	2		T5	16
valid_sources[0x20]	8322	1			T1	34		T3	4		T4	2
valid_sources[0x21]	7828	1			T1	26		T3	19		T4	2
valid_sources[0x22]	8270	1			T1	43		T3	17		T5	13
valid_sources[0x23]	8164	1			T1	32		T3	3		T4	12
valid_sources[0x24]	11008	1			T1	41		T3	4		T4	12
valid_sources[0x25]	6637	1			T1	32		T3	6		T4	4
valid_sources[0x26]	15114	1			T1	25		T3	2		T4	1
valid_sources[0x27]	8997	1			T1	29		T3	24		T4	5
valid_sources[0x28]	6900	1			T1	39		T3	3		T4	3
valid_sources[0x29]	7532	1			T1	22		T5	14		T6	1
valid_sources[0x2a]	6639	1			T1	46		T3	7		T5	20
valid_sources[0x2b]	6454	1			T1	40		T3	2		T4	5
valid_sources[0x2c]	20088	1			T1	33		T3	6		T4	1
valid_sources[0x2d]	6560	1			T1	22		T3	8		T4	5
valid_sources[0x2e]	6683	1			T1	40		T3	4		T4	1
valid_sources[0x2f]	7290	1			T1	25		T3	2		T4	1
valid_sources[0x30]	12747	1			T1	23		T3	12		T4	2
valid_sources[0x31]	8781	1			T1	42		T3	4		T4	12
valid_sources[0x32]	7833	1			T1	34		T3	12		T4	3
valid_sources[0x33]	9033	1			T1	28		T3	5		T4	10
valid_sources[0x34]	9351	1			T1	35		T3	8		T4	5
valid_sources[0x35]	12239	1			T1	33		T3	15		T5	24
valid_sources[0x36]	7809	1			T1	29		T3	5		T4	9
valid_sources[0x37]	7032	1			T1	33		T3	4		T5	23
valid_sources[0x38]	9615	1			T1	49		T3	15		T4	3
valid_sources[0x39]	6210	1			T1	52		T3	5		T5	13
valid_sources[0x3a]	8431	1			T1	28		T3	6		T4	2
valid_sources[0x3b]	6525	1			T1	32		T3	8		T5	17
valid_sources[0x3c]	9551	1			T1	27		T3	2		T5	17
valid_sources[0x3d]	6580	1			T1	36		T3	3		T4	3
valid_sources[0x3e]	7545	1			T1	37		T3	6		T5	26
valid_sources[0x3f]	8185	1			T1	34		T3	8		T4	3
valid_sources[0x40]	9125	1			T1	45		T3	9		T5	17
valid_sources[0x41]	11398	1			T1	27		T3	23		T5	11
valid_sources[0x42]	9924	1			T1	44		T3	3		T4	6
valid_sources[0x43]	10995	1			T1	21		T3	3		T4	1
valid_sources[0x44]	6574	1			T1	34		T3	2		T4	3
valid_sources[0x45]	7425	1			T1	35		T3	3		T4	5
valid_sources[0x46]	7842	1			T1	36		T3	4		T5	15
valid_sources[0x47]	7346	1			T1	35		T3	11		T5	17
valid_sources[0x48]	6237	1			T1	34		T3	7		T4	2
valid_sources[0x49]	6609	1			T1	46		T3	8		T4	13
valid_sources[0x4a]	16084	1			T1	32		T3	3		T5	19
valid_sources[0x4b]	12264	1			T1	39		T3	971		T4	3
valid_sources[0x4c]	14920	1			T1	32		T3	3		T5	12
valid_sources[0x4d]	6991	1			T1	30		T3	1		T5	22
valid_sources[0x4e]	13335	1			T1	19		T3	14		T4	18
valid_sources[0x4f]	7611	1			T1	28		T3	6		T5	10
valid_sources[0x50]	6395	1			T1	24		T3	21		T4	5
valid_sources[0x51]	6906	1			T1	37		T3	5		T4	10
valid_sources[0x52]	7687	1			T1	27		T3	2		T4	1
valid_sources[0x53]	10549	1			T1	18		T3	10		T4	4
valid_sources[0x54]	6599	1			T1	34		T3	8		T4	5
valid_sources[0x55]	6926	1			T1	30		T3	1		T5	15
valid_sources[0x56]	7410	1			T1	39		T3	3		T5	21
valid_sources[0x57]	6655	1			T1	45		T3	2		T4	3
valid_sources[0x58]	7508	1			T1	34		T3	4		T5	19
valid_sources[0x59]	10178	1			T1	30		T3	7		T5	21
valid_sources[0x5a]	7259	1			T1	27		T3	29		T5	13
valid_sources[0x5b]	8297	1			T1	28		T3	4		T4	8
valid_sources[0x5c]	6655	1			T1	43		T3	17		T4	7
valid_sources[0x5d]	11308	1			T1	43		T4	6		T5	30
valid_sources[0x5e]	7556	1			T1	32		T3	5		T4	1
valid_sources[0x5f]	7762	1			T1	47		T3	6		T4	3
valid_sources[0x60]	19473	1			T1	30		T3	2		T5	20
valid_sources[0x61]	7936	1			T1	51		T3	4		T4	2
valid_sources[0x62]	11029	1			T1	42		T3	3		T5	10
valid_sources[0x63]	11053	1			T1	23		T3	4		T4	1
valid_sources[0x64]	16137	1			T1	27		T3	2		T5	21
valid_sources[0x65]	6315	1			T1	29		T3	4		T5	14
valid_sources[0x66]	6877	1			T1	30		T3	1		T4	6
valid_sources[0x67]	11285	1			T1	47		T3	6		T4	6
valid_sources[0x68]	6560	1			T1	21		T3	3		T5	16
valid_sources[0x69]	11211	1			T1	23		T3	5		T5	16
valid_sources[0x6a]	11110	1			T1	25		T3	2		T4	3
valid_sources[0x6b]	6906	1			T1	37		T3	3		T4	6
valid_sources[0x6c]	6735	1			T1	34		T3	4		T5	19
valid_sources[0x6d]	6506	1			T1	36		T3	4		T5	19
valid_sources[0x6e]	10954	1			T1	34		T3	1		T4	3
valid_sources[0x6f]	11844	1			T1	39		T3	3		T4	4
valid_sources[0x70]	13497	1			T1	30		T3	16		T4	9
valid_sources[0x71]	6495	1			T1	49		T3	5		T4	7
valid_sources[0x72]	7726	1			T1	45		T3	2		T5	22
valid_sources[0x73]	7308	1			T1	32		T3	6		T4	12
valid_sources[0x74]	10659	1			T1	36		T3	3		T4	6
valid_sources[0x75]	6413	1			T1	30		T3	27		T4	1
valid_sources[0x76]	7780	1			T1	32		T3	3		T4	7
valid_sources[0x77]	10856	1			T1	28		T3	12		T4	2
valid_sources[0x78]	7125	1			T1	42		T3	3		T4	4
valid_sources[0x79]	7346	1			T1	23		T3	7		T4	3
valid_sources[0x7a]	6473	1			T1	32		T3	7		T4	6
valid_sources[0x7b]	7149	1			T1	33		T3	12		T4	1
valid_sources[0x7c]	6559	1			T1	34		T3	7		T4	9
valid_sources[0x7d]	10822	1			T1	36		T3	6		T4	2
valid_sources[0x7e]	6765	1			T1	28		T3	5		T4	1
valid_sources[0x7f]	10602	1			T1	34		T3	11		T4	12
valid_sources[0x80]	6768	1			T1	32		T3	12		T4	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1014347

1

T1

4106

T3

1239

T4

410

values[0x0]

all_enables

biggest_size

83720

1

T1

108

T2

16

T3

88

values[0x1]

all_enables

biggest_size

60281

1

T1

72

T2

6

T3

52