Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31675	1			T1	19		T3	24		T4	7
auto[PWRUP]	139	1			T9	1		T45	3		T44	1
auto[ONEST_0]	97	1			T44	1		T48	1		T38	2
auto[ONEST_021]	18	1			T48	1		T200	1		T201	1
auto[ONEST_1]	91	1			T45	2		T48	2		T46	1
auto[ONEST_DONE]	4	1			T202	1		T203	1		T204	1
auto[LP_0]	121	1			T45	1		T48	1		T46	3
auto[LP_021]	39	1			T44	1		T46	1		T38	1
auto[LP_1]	141	1			T45	2		T48	1		T46	2
auto[LP_EVAL]	73	1			T6	1		T45	1		T44	2
auto[LP_SLP]	593	1			T6	1		T9	3		T45	5
auto[LP_PWRUP]	28	1			T49	1		T16	1		T173	2
auto[NP_0]	183	1			T9	1		T45	1		T44	1
auto[NP_021]	40	1			T14	1		T173	1		T153	2
auto[NP_1]	190	1			T45	3		T44	1		T48	1
auto[NP_EVAL]	38	1			T46	1		T16	1		T173	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T205

1

T202

1

T206

1

min

31011

1

T1

19

T3

24

T4

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31019	1			T1	19		T3	24		T4	7
pow[0x1]	7	1			T9	1		T14	1		T207	1
pow[0x2]	26	1			T46	1		T14	1		T208	1
pow[0x3]	47	1			T44	2		T46	1		T14	1
pow[0x4]	86	1			T6	1		T45	1		T44	2
pow[0x5]	168	1			T9	1		T45	1		T44	3
pow[0x6]	321	1			T9	1		T45	3		T44	2
pow[0x7]	623	1			T6	1		T9	2		T45	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

227

1

T9

1

T45

1

T44

2

min

30472

1

T1

19

T3

24

T4

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30472	1			T1	19		T3	24		T4	7
pow[0x4]	2	1			T209	1		T210	1		-	-
pow[0x6]	2	1			T211	1		T212	1		-	-
pow[0x7]	5	1			T173	2		T213	1		T214	1
pow[0x8]	8	1			T215	1		T216	1		T217	1
pow[0x9]	11	1			T14	1		T213	1		T218	1
pow[0xa]	22	1			T50	1		T16	2		T173	1
pow[0xb]	47	1			T44	1		T50	1		T15	1
pow[0xc]	91	1			T44	1		T46	1		T38	1
pow[0xd]	161	1			T6	1		T9	1		T45	1
pow[0xe]	327	1			T9	1		T45	5		T44	3
pow[0xf]	709	1			T6	2		T9	3		T45	6