Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2603	1			T6	13		T9	21		T33	7
auto[PWRUP]	136	1			T9	2		T45	2		T44	1
auto[ONEST_0]	92	1			T9	1		T48	1		T46	2
auto[ONEST_021]	21	1			T46	2		T173	2		T207	2
auto[ONEST_1]	98	1			T9	1		T14	1		T50	1
auto[ONEST_DONE]	2	1			T348	1		T349	1		-	-
auto[LP_0]	143	1			T45	2		T46	2		T14	1
auto[LP_021]	38	1			T16	1		T144	1		T173	2
auto[LP_1]	208	1			T9	3		T12	1		T13	1
auto[LP_EVAL]	57	1			T9	1		T44	1		T48	1
auto[LP_SLP]	628	1			T6	4		T9	3		T45	5
auto[LP_PWRUP]	33	1			T48	1		T14	1		T208	1
auto[NP_0]	276	1			T6	2		T9	3		T45	2
auto[NP_021]	57	1			T9	2		T45	1		T44	1
auto[NP_1]	244	1			T6	2		T9	1		T33	1
auto[NP_EVAL]	36	1			T33	2		T12	1		T37	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T348

1

T350

1

T351

2

min

2197

1

T6

16

T9

20

T33

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2213	1			T6	18		T9	20		T33	10
pow[0x1]	15	1			T208	2		T173	1		T352	1
pow[0x2]	26	1			T48	1		T46	1		T50	1
pow[0x3]	45	1			T9	1		T13	1		T50	1
pow[0x4]	56	1			T45	1		T44	1		T46	2
pow[0x5]	172	1			T9	1		T45	2		T48	5
pow[0x6]	283	1			T9	2		T45	2		T44	2
pow[0x7]	609	1			T6	2		T9	2		T45	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

237

1

T9

1

T45

5

T44

3

min

1498

1

T6

15

T9

19

T33

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1503	1			T6	15		T9	19		T33	8
pow[0x1]	9	1			T9	1		T144	1		T173	1
pow[0x2]	29	1			T33	1		T12	1		T36	2
pow[0x3]	40	1			T12	3		T37	1		T14	2
pow[0x4]	76	1			T6	3		T33	1		T36	2
pow[0x5]	1	1			T353	1		-	-		-	-
pow[0x6]	2	1			T46	1		T348	1		-	-
pow[0x7]	4	1			T16	1		T200	1		T265	1
pow[0x8]	6	1			T50	1		T213	1		T200	1
pow[0x9]	11	1			T6	1		T45	1		T200	1
pow[0xa]	12	1			T153	1		T200	1		T354	2
pow[0xb]	48	1			T6	1		T14	2		T49	1
pow[0xc]	94	1			T48	3		T46	1		T14	1
pow[0xd]	189	1			T45	1		T44	1		T48	2
pow[0xe]	355	1			T6	1		T9	1		T45	4
pow[0xf]	676	1			T9	6		T45	3		T44	6