Unified Coverage Report :: Module :: adc_ctrl_fsm

Module : adc_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.94	100.00	96.84		100.00	92.86	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.75	100.00	100.00		100.00	98.73	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.75	100.00	100.00		100.00	98.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_adc_ctrl_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm_sva	100.00						100.00

Line Coverage for Module : adc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		162	162	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	61	5	5	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	103	5	5	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	117	5	5	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
ALWAYS	136	14	14	100.00
ALWAYS	157	6	6	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
ALWAYS	176	5	5	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	95	95	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
61	1	1
62	1	1
64	1	1
65	1	1
67	1	1
71	1	1
72	1	1
74	1	1
77	1	1
78	1	1
80	1	1
81	1	1
83	1	1
87	1	1
90	1	1
91	1	1
93	1	1
94	1	1
96	1	1
100	1	1
103	1	1
104	1	1
106	1	1
107	1	1
109	1	1
113	1	1
117	1	1
118	1	1
120	1	1
121	1	1
123	1	1
127	1	1
128	1	1
129	1	1
131	1	1
132	1	1
133	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
148	1	1
149	1	1
150	1	1
151	1	1
157	1	1
158	1	1
160	1	1
161	1	1
163	1	1
164	1	1
			MISSING_ELSE
169	1	1
173	1	1
176	1	1
177	1	1
179	1	1
180	1	1
182	1	1
186	1	1
187	1	1
190	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
207	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
219	1	1
220	1	1
221	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
241	1	1
242	1	1
			MISSING_ELSE
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
256	1	1
257	1	1
261	1	1
262	1	1
263	1	1
			MISSING_ELSE
268	1	1
269	1	1
			MISSING_ELSE
274	1	1
275	1	1
276	1	1
			MISSING_ELSE
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
			MISSING_ELSE
			MISSING_ELSE
299	1	1
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
			==> MISSING_ELSE
310	1	1
311	1	1
313	1	1
314	1	1
315	1	1
			==> MISSING_ELSE
320	1	1
321	1	1
322	1	1
			MISSING_ELSE
327	1	1
328	1	1
			MISSING_ELSE
333	1	1
334	1	1
335	1	1
			MISSING_ELSE
341	1	1
342	1	1
353	1	1
354	1	1
355	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
			==> MISSING_ELSE
			MISSING_ELSE
374	1	1
375	1	1

---

Cond Coverage for Module : adc_ctrl_fsm

	Total	Covered	Percent
Conditions	95	92	96.84
Logical	95	92	96.84
Non-Logical	0	0
Event	0	0

 LINE       71
 EXPRESSION ((trigger_q == 1'b0) && (cfg_adc_enable_i == 1'b1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (trigger_q == 1'b0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cfg_adc_enable_i == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION ((trigger_q == 1'b1) && (cfg_adc_enable_i == 1'b0))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (trigger_q == 1'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (cfg_adc_enable_i == 1'b0)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (pwrup_timer_cnt_en ? ((pwrup_timer_cnt_q + 1'b1)) : pwrup_timer_cnt_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             ---------1---------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (lp_sample_cnt_en ? ((lp_sample_cnt_q + 1'b1)) : lp_sample_cnt_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       93
 EXPRESSION (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             --------1--------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (np_sample_cnt_en ? ((np_sample_cnt_q + 1'b1)) : np_sample_cnt_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       106
 EXPRESSION (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             --------1--------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (wakeup_timer_cnt_en ? ((wakeup_timer_cnt_q + 1'b1)) : wakeup_timer_cnt_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       120
 EXPRESSION (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             ----------1---------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T4,T5,T6

 LINE       127
 EXPRESSION ((fsm_state_q == ONEST_0) || (fsm_state_q == LP_0) || (fsm_state_q == NP_0))
             ------------1-----------    ----------2----------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T2,T6,T9

 LINE       127
 SUB-EXPRESSION (fsm_state_q == ONEST_0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T9

 LINE       127
 SUB-EXPRESSION (fsm_state_q == LP_0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       127
 SUB-EXPRESSION (fsm_state_q == NP_0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION (fsm_chn0_sel && adc_d_val_i)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (chn0_val_we_d ? adc_d_i : chn0_val_o)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION ((fsm_state_q == ONEST_1) || (fsm_state_q == LP_1) || (fsm_state_q == NP_1))
             ------------1-----------    ----------2----------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T2,T6,T9

 LINE       131
 SUB-EXPRESSION (fsm_state_q == ONEST_1)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T9

 LINE       131
 SUB-EXPRESSION (fsm_state_q == LP_1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       131
 SUB-EXPRESSION (fsm_state_q == NP_1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fsm_chn1_sel && adc_d_val_i)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (chn1_val_we_d ? adc_d_i : chn1_val_o)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       169
 EXPRESSION (((|adc_ctrl_match_i)) & ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q))))
             ----------1----------   --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       169
 SUB-EXPRESSION ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q)))
                 -------------------1------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       169
 SUB-EXPRESSION (adc_ctrl_match_i == adc_ctrl_match_q)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (trigger_h2l || cfg_fsm_rst_i)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       216
 EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (lp_sample_cnt_q == lp_sample_cnt_thresh)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T6,T9,T44
1	Covered	T4,T5,T9

 LINE       300
 EXPRESSION (wakeup_timer_cnt_q != cfg_wakeup_time_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       303
 EXPRESSION (wakeup_timer_cnt_q == cfg_wakeup_time_i)
            --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       310
 EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       313
 EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION (np_sample_cnt_q == np_sample_cnt_thresh)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

---

FSM Coverage for Module : adc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	17	17	100.00	(Not included in score)
Transitions	37	37	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
LP_0	225	Covered	T4,T5,T6
LP_021	263	Covered	T4,T5,T6
LP_1	269	Covered	T4,T5,T6
LP_EVAL	276	Covered	T4,T5,T6
LP_PWRUP	304	Covered	T4,T5,T6
LP_SLP	285	Covered	T4,T5,T6
NP_0	228	Covered	T1,T2,T3
NP_021	322	Covered	T1,T2,T3
NP_1	328	Covered	T1,T2,T3
NP_DONE	364	Covered	T1,T3,T4
NP_EVAL	335	Covered	T1,T2,T3
ONEST_0	222	Covered	T2,T6,T9
ONEST_021	236	Covered	T2,T6,T9
ONEST_1	242	Covered	T2,T6,T9
ONEST_DONE	249	Covered	T2,T6,T9
PWRDN	180	Covered	T1,T2,T3
PWRUP	211	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
LP_0->LP_021	263	Covered	T4,T5,T6
LP_0->PWRDN	180	Covered	T11,T34,T45
LP_021->LP_1	269	Covered	T4,T5,T6
LP_021->PWRDN	180	Covered	T44,T46,T38
LP_1->LP_EVAL	276	Covered	T4,T5,T6
LP_1->PWRDN	180	Covered	T9,T45,T12
LP_EVAL->LP_SLP	285	Covered	T4,T5,T6
LP_EVAL->NP_0	291	Covered	T4,T5,T9
LP_EVAL->PWRDN	180	Covered	T6,T9,T47
LP_PWRUP->LP_0	315	Covered	T4,T5,T6
LP_PWRUP->PWRDN	180	Covered	T48,T14,T49
LP_SLP->LP_PWRUP	304	Covered	T4,T5,T6
LP_SLP->PWRDN	180	Covered	T6,T9,T47
NP_0->NP_021	322	Covered	T1,T2,T3
NP_0->PWRDN	180	Covered	T1,T2,T3
NP_021->NP_1	328	Covered	T1,T2,T3
NP_021->PWRDN	180	Covered	T9,T45,T44
NP_1->NP_EVAL	335	Covered	T1,T2,T3
NP_1->PWRDN	180	Covered	T6,T9,T33
NP_DONE->NP_0	375	Covered	T1,T3,T4
NP_DONE->PWRDN	180	Covered	T44,T14,T50
NP_EVAL->LP_0	355	Covered	T4,T5,T9
NP_EVAL->NP_0	357	Covered	T1,T2,T3
NP_EVAL->NP_DONE	364	Covered	T1,T3,T4
NP_EVAL->PWRDN	180	Covered	T2,T9,T33
ONEST_0->ONEST_021	236	Covered	T2,T6,T9
ONEST_0->PWRDN	180	Covered	T6,T9,T45
ONEST_021->ONEST_1	242	Covered	T2,T6,T9
ONEST_021->PWRDN	180	Covered	T45,T48,T46
ONEST_1->ONEST_DONE	249	Covered	T2,T6,T9
ONEST_1->PWRDN	180	Covered	T9,T45,T48
ONEST_DONE->PWRDN	180	Covered	T2,T6,T9
PWRDN->PWRUP	211	Covered	T1,T2,T3
PWRUP->LP_0	225	Covered	T4,T5,T6
PWRUP->NP_0	228	Covered	T1,T2,T3
PWRUP->ONEST_0	222	Covered	T2,T6,T9
PWRUP->PWRDN	180	Covered	T6,T9,T45

---

Branch Coverage for Module : adc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		84	78	92.86
TERNARY	74	2	2	100.00
TERNARY	87	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	113	2	2	100.00
TERNARY	129	2	2	100.00
TERNARY	133	2	2	100.00
IF	61	3	3	100.00
IF	77	3	3	100.00
IF	90	3	3	100.00
IF	103	3	3	100.00
IF	117	3	3	100.00
IF	136	3	3	100.00
IF	157	4	4	100.00
IF	176	3	3	100.00
CASE	207	47	41	87.23

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(pwrup_timer_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	(lp_sample_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	(np_sample_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	113	(wakeup_timer_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	(chn0_val_we_d) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	133	(chn1_val_we_d) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	61	if ((!rst_aon_ni))
-2-:	64	if (cfg_fsm_rst_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if ((!rst_aon_ni))
-2-:	80	if (((pwrup_timer_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	if ((!rst_aon_ni))
-2-:	93	if (((lp_sample_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	103	if ((!rst_aon_ni))
-2-:	106	if (((np_sample_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_aon_ni))
-2-:	120	if (((wakeup_timer_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if ((!rst_aon_ni))
-2-:	142	if (cfg_fsm_rst_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if ((!rst_aon_ni))
-2-:	160	if (cfg_fsm_rst_i)
-3-:	163	if (ld_match)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	if ((!rst_aon_ni))
-2-:	179	if ((trigger_h2l || cfg_fsm_rst_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	207	case (fsm_state_q)
-2-:	210	if (trigger_l2h)
-3-:	216	if ((pwrup_timer_cnt_q != cfg_pwrup_time_i))
-4-:	219	if ((pwrup_timer_cnt_q == cfg_pwrup_time_i))
-5-:	221	if (cfg_oneshot_mode_i)
-6-:	224	if (cfg_lp_mode_i)
-7-:	227	if ((!cfg_lp_mode_i))
-8-:	235	if (adc_d_val_i)
-9-:	241	if ((!adc_d_val_i))
-10-:	248	if (adc_d_val_i)
-11-:	262	if (adc_d_val_i)
-12-:	268	if ((!adc_d_val_i))
-13-:	275	if (adc_d_val_i)
-14-:	282	if ((!adc_d_val_i))
-15-:	284	if ((!stay_match))
-16-:	287	if ((lp_sample_cnt_q < lp_sample_cnt_thresh))
-17-:	290	if ((lp_sample_cnt_q == lp_sample_cnt_thresh))
-18-:	300	if ((wakeup_timer_cnt_q != cfg_wakeup_time_i))
-19-:	303	if ((wakeup_timer_cnt_q == cfg_wakeup_time_i))
-20-:	310	if ((pwrup_timer_cnt_q != cfg_pwrup_time_i))
-21-:	313	if ((pwrup_timer_cnt_q == cfg_pwrup_time_i))
-22-:	321	if (adc_d_val_i)
-23-:	327	if ((!adc_d_val_i))
-24-:	334	if (adc_d_val_i)
-25-:	341	if ((!adc_d_val_i))
-26-:	353	if ((!stay_match))
-27-:	354	if (cfg_lp_mode_i)
-28-:	360	if ((np_sample_cnt_q < np_sample_cnt_thresh))
-29-:	363	if ((np_sample_cnt_q == np_sample_cnt_thresh))
-30-:	366	if ((np_sample_cnt_q > np_sample_cnt_thresh))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
PWRDN	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRDN	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
PWRUP	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
PWRUP	-	0	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
PWRUP	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ONEST_0	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_0	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_021	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_021	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_1	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_1	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_DONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
LP_0	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_0	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_021	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_021	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_1	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_1	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T9,T44
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	Not Covered
NP_0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_021	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_021	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
NP_1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T5,T9
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	1	-	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	0	1	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	0	0	Not Covered
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
NP_DONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : adc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LpSampleCntCfg_M	31224689	31138496	0	0
NpCntClrMisMatch_A	31224689	159633	0	0
NpCntClrPwrDn_A	31224689	93676	0	0
NpSampleCntCfg_M	31224689	31138496	0	0

LpSampleCntCfg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	31138496	0	0
T1	66900	66845	0	0
T2	786	722	0	0
T3	99572	99513	0	0
T4	32568	32475	0	0
T5	38082	38021	0	0
T6	90	1	0	0
T7	33623	33542	0	0
T8	33277	33191	0	0
T9	49529	48998	0	0
T10	67855	67755	0	0

NpCntClrMisMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	159633	0	0
T1	66900	696	0	0
T2	786	12	0	0
T3	99572	836	0	0
T4	32568	16	0	0
T5	38082	161	0	0
T6	90	0	0	0
T7	33623	68	0	0
T8	33277	54	0	0
T9	49529	212	0	0
T10	67855	37	0	0
T11	0	25	0	0

NpCntClrPwrDn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	93676	0	0
T1	66900	139	0	0
T2	786	85	0	0
T3	99572	192	0	0
T4	32568	76	0	0
T5	38082	70	0	0
T6	90	1	0	0
T7	33623	81	0	0
T8	33277	74	0	0
T9	49529	91	0	0
T10	67855	137	0	0

NpSampleCntCfg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	31138496	0	0
T1	66900	66845	0	0
T2	786	722	0	0
T3	99572	99513	0	0
T4	32568	32475	0	0
T5	38082	38021	0	0
T6	90	1	0	0
T7	33623	33542	0	0
T8	33277	33191	0	0
T9	49529	48998	0	0
T10	67855	67755	0	0

Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		162	162	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	61	5	5	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	103	5	5	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	117	5	5	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
ALWAYS	136	14	14	100.00
ALWAYS	157	6	6	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
ALWAYS	176	5	5	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	95	95	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
61	1	1
62	1	1
64	1	1
65	1	1
67	1	1
71	1	1
72	1	1
74	1	1
77	1	1
78	1	1
80	1	1
81	1	1
83	1	1
87	1	1
90	1	1
91	1	1
93	1	1
94	1	1
96	1	1
100	1	1
103	1	1
104	1	1
106	1	1
107	1	1
109	1	1
113	1	1
117	1	1
118	1	1
120	1	1
121	1	1
123	1	1
127	1	1
128	1	1
129	1	1
131	1	1
132	1	1
133	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
148	1	1
149	1	1
150	1	1
151	1	1
157	1	1
158	1	1
160	1	1
161	1	1
163	1	1
164	1	1
			MISSING_ELSE
169	1	1
173	1	1
176	1	1
177	1	1
179	1	1
180	1	1
182	1	1
186	1	1
187	1	1
190	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
207	1	1
209	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
219	1	1
220	1	1
221	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
241	1	1
242	1	1
			MISSING_ELSE
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
256	1	1
257	1	1
261	1	1
262	1	1
263	1	1
			MISSING_ELSE
268	1	1
269	1	1
			MISSING_ELSE
274	1	1
275	1	1
276	1	1
			MISSING_ELSE
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
			MISSING_ELSE
			MISSING_ELSE
299	1	1
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
			==> MISSING_ELSE
310	1	1
311	1	1
313	1	1
314	1	1
315	1	1
			==> MISSING_ELSE
320	1	1
321	1	1
322	1	1
			MISSING_ELSE
327	1	1
328	1	1
			MISSING_ELSE
333	1	1
334	1	1
335	1	1
			MISSING_ELSE
341	1	1
342	1	1
353	1	1
354	1	1
355	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
			==> MISSING_ELSE
			MISSING_ELSE
374	1	1
375	1	1

---

Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm

	Total	Covered	Percent
Conditions	92	92	100.00
Logical	92	92	100.00
Non-Logical	0	0
Event	0	0

 LINE       71
 EXPRESSION ((trigger_q == 1'b0) && (cfg_adc_enable_i == 1'b1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (trigger_q == 1'b0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cfg_adc_enable_i == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION ((trigger_q == 1'b1) && (cfg_adc_enable_i == 1'b0))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (trigger_q == 1'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (cfg_adc_enable_i == 1'b0)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (pwrup_timer_cnt_en ? ((pwrup_timer_cnt_q + 1'b1)) : pwrup_timer_cnt_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             ---------1---------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (lp_sample_cnt_en ? ((lp_sample_cnt_q + 1'b1)) : lp_sample_cnt_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       93
 EXPRESSION (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             --------1--------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (np_sample_cnt_en ? ((np_sample_cnt_q + 1'b1)) : np_sample_cnt_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       106
 EXPRESSION (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             --------1--------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (wakeup_timer_cnt_en ? ((wakeup_timer_cnt_q + 1'b1)) : wakeup_timer_cnt_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       120
 EXPRESSION (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
             ----------1---------    ------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T4,T5,T6

 LINE       127
 EXPRESSION ((fsm_state_q == ONEST_0) || (fsm_state_q == LP_0) || (fsm_state_q == NP_0))
             ------------1-----------    ----------2----------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T2,T6,T9

 LINE       127
 SUB-EXPRESSION (fsm_state_q == ONEST_0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T9

 LINE       127
 SUB-EXPRESSION (fsm_state_q == LP_0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       127
 SUB-EXPRESSION (fsm_state_q == NP_0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION (fsm_chn0_sel && adc_d_val_i)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (chn0_val_we_d ? adc_d_i : chn0_val_o)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION ((fsm_state_q == ONEST_1) || (fsm_state_q == LP_1) || (fsm_state_q == NP_1))
             ------------1-----------    ----------2----------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T4,T5,T6
1	0	0	Covered	T2,T6,T9

 LINE       131
 SUB-EXPRESSION (fsm_state_q == ONEST_1)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T9

 LINE       131
 SUB-EXPRESSION (fsm_state_q == LP_1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       131
 SUB-EXPRESSION (fsm_state_q == NP_1)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (fsm_chn1_sel && adc_d_val_i)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (chn1_val_we_d ? adc_d_i : chn1_val_o)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       169
 EXPRESSION (((|adc_ctrl_match_i)) & ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q))))
             ----------1----------   --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       169
 SUB-EXPRESSION ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q)))
                 -------------------1------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       169
 SUB-EXPRESSION (adc_ctrl_match_i == adc_ctrl_match_q)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (trigger_h2l || cfg_fsm_rst_i)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       216
 EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (lp_sample_cnt_q == lp_sample_cnt_thresh)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T6,T9,T44
1	Covered	T4,T5,T9

 LINE       300
 EXPRESSION (wakeup_timer_cnt_q != cfg_wakeup_time_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       303
 EXPRESSION (wakeup_timer_cnt_q == cfg_wakeup_time_i)
            --------------------1--------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T4,T5,T6

 LINE       310
 EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       313
 EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
            -------------------1-------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T4,T5,T6

 LINE       363
 EXPRESSION (np_sample_cnt_q == np_sample_cnt_thresh)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	17	17	100.00	(Not included in score)
Transitions	37	37	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
LP_0	225	Covered	T4,T5,T6
LP_021	263	Covered	T4,T5,T6
LP_1	269	Covered	T4,T5,T6
LP_EVAL	276	Covered	T4,T5,T6
LP_PWRUP	304	Covered	T4,T5,T6
LP_SLP	285	Covered	T4,T5,T6
NP_0	228	Covered	T1,T2,T3
NP_021	322	Covered	T1,T2,T3
NP_1	328	Covered	T1,T2,T3
NP_DONE	364	Covered	T1,T3,T4
NP_EVAL	335	Covered	T1,T2,T3
ONEST_0	222	Covered	T2,T6,T9
ONEST_021	236	Covered	T2,T6,T9
ONEST_1	242	Covered	T2,T6,T9
ONEST_DONE	249	Covered	T2,T6,T9
PWRDN	180	Covered	T1,T2,T3
PWRUP	211	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
LP_0->LP_021	263	Covered	T4,T5,T6
LP_0->PWRDN	180	Covered	T11,T34,T45
LP_021->LP_1	269	Covered	T4,T5,T6
LP_021->PWRDN	180	Covered	T44,T46,T38
LP_1->LP_EVAL	276	Covered	T4,T5,T6
LP_1->PWRDN	180	Covered	T9,T45,T12
LP_EVAL->LP_SLP	285	Covered	T4,T5,T6
LP_EVAL->NP_0	291	Covered	T4,T5,T9
LP_EVAL->PWRDN	180	Covered	T6,T9,T47
LP_PWRUP->LP_0	315	Covered	T4,T5,T6
LP_PWRUP->PWRDN	180	Covered	T48,T14,T49
LP_SLP->LP_PWRUP	304	Covered	T4,T5,T6
LP_SLP->PWRDN	180	Covered	T6,T9,T47
NP_0->NP_021	322	Covered	T1,T2,T3
NP_0->PWRDN	180	Covered	T1,T2,T3
NP_021->NP_1	328	Covered	T1,T2,T3
NP_021->PWRDN	180	Covered	T9,T45,T44
NP_1->NP_EVAL	335	Covered	T1,T2,T3
NP_1->PWRDN	180	Covered	T6,T9,T33
NP_DONE->NP_0	375	Covered	T1,T3,T4
NP_DONE->PWRDN	180	Covered	T44,T14,T50
NP_EVAL->LP_0	355	Covered	T4,T5,T9
NP_EVAL->NP_0	357	Covered	T1,T2,T3
NP_EVAL->NP_DONE	364	Covered	T1,T3,T4
NP_EVAL->PWRDN	180	Covered	T2,T9,T33
ONEST_0->ONEST_021	236	Covered	T2,T6,T9
ONEST_0->PWRDN	180	Covered	T6,T9,T45
ONEST_021->ONEST_1	242	Covered	T2,T6,T9
ONEST_021->PWRDN	180	Covered	T45,T48,T46
ONEST_1->ONEST_DONE	249	Covered	T2,T6,T9
ONEST_1->PWRDN	180	Covered	T9,T45,T48
ONEST_DONE->PWRDN	180	Covered	T2,T6,T9
PWRDN->PWRUP	211	Covered	T1,T2,T3
PWRUP->LP_0	225	Covered	T4,T5,T6
PWRUP->NP_0	228	Covered	T1,T2,T3
PWRUP->ONEST_0	222	Covered	T2,T6,T9
PWRUP->PWRDN	180	Covered	T6,T9,T45

---

Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		79	78	98.73
TERNARY	74	2	2	100.00
TERNARY	87	2	2	100.00
TERNARY	100	2	2	100.00
TERNARY	113	2	2	100.00
TERNARY	129	2	2	100.00
TERNARY	133	2	2	100.00
IF	61	3	3	100.00
IF	77	3	3	100.00
IF	90	3	3	100.00
IF	103	3	3	100.00
IF	117	3	3	100.00
IF	136	3	3	100.00
IF	157	4	4	100.00
IF	176	3	3	100.00
CASE	207	42	41	97.62

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(pwrup_timer_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	(lp_sample_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	(np_sample_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	113	(wakeup_timer_cnt_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	(chn0_val_we_d) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	133	(chn1_val_we_d) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	61	if ((!rst_aon_ni))
-2-:	64	if (cfg_fsm_rst_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if ((!rst_aon_ni))
-2-:	80	if (((pwrup_timer_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	if ((!rst_aon_ni))
-2-:	93	if (((lp_sample_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	103	if ((!rst_aon_ni))
-2-:	106	if (((np_sample_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_aon_ni))
-2-:	120	if (((wakeup_timer_cnt_clr || cfg_fsm_rst_i) || trigger_h2l))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if ((!rst_aon_ni))
-2-:	142	if (cfg_fsm_rst_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if ((!rst_aon_ni))
-2-:	160	if (cfg_fsm_rst_i)
-3-:	163	if (ld_match)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	if ((!rst_aon_ni))
-2-:	179	if ((trigger_h2l || cfg_fsm_rst_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	207	case (fsm_state_q)
-2-:	210	if (trigger_l2h)
-3-:	216	if ((pwrup_timer_cnt_q != cfg_pwrup_time_i))
-4-:	219	if ((pwrup_timer_cnt_q == cfg_pwrup_time_i))
-5-:	221	if (cfg_oneshot_mode_i)
-6-:	224	if (cfg_lp_mode_i)
-7-:	227	if ((!cfg_lp_mode_i))
-8-:	235	if (adc_d_val_i)
-9-:	241	if ((!adc_d_val_i))
-10-:	248	if (adc_d_val_i)
-11-:	262	if (adc_d_val_i)
-12-:	268	if ((!adc_d_val_i))
-13-:	275	if (adc_d_val_i)
-14-:	282	if ((!adc_d_val_i))
-15-:	284	if ((!stay_match))
-16-:	287	if ((lp_sample_cnt_q < lp_sample_cnt_thresh))
-17-:	290	if ((lp_sample_cnt_q == lp_sample_cnt_thresh))
-18-:	300	if ((wakeup_timer_cnt_q != cfg_wakeup_time_i))
-19-:	303	if ((wakeup_timer_cnt_q == cfg_wakeup_time_i))
-20-:	310	if ((pwrup_timer_cnt_q != cfg_pwrup_time_i))
-21-:	313	if ((pwrup_timer_cnt_q == cfg_pwrup_time_i))
-22-:	321	if (adc_d_val_i)
-23-:	327	if ((!adc_d_val_i))
-24-:	334	if (adc_d_val_i)
-25-:	341	if ((!adc_d_val_i))
-26-:	353	if ((!stay_match))
-27-:	354	if (cfg_lp_mode_i)
-28-:	360	if ((np_sample_cnt_q < np_sample_cnt_thresh))
-29-:	363	if ((np_sample_cnt_q == np_sample_cnt_thresh))
-30-:	366	if ((np_sample_cnt_q > np_sample_cnt_thresh))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests	Exclude Annotation
PWRDN	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRDN	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
PWRUP	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
PWRUP	-	0	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PWRUP	-	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
PWRUP	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
ONEST_0	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_0	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_021	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_021	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_1	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_1	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
ONEST_DONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T9
LP_0	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_0	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_021	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_021	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_1	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_1	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T9,T44
LP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_SLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
LP_PWRUP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
NP_0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_021	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_021	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
NP_1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
NP_1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T5,T9
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	1	-	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	0	1	Covered	T1,T3,T4
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	0	0	Excluded		VC_COV_UNR
NP_EVAL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
NP_DONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
LpSampleCntCfg_M	31224689	31138496	0	0
NpCntClrMisMatch_A	31224689	159633	0	0
NpCntClrPwrDn_A	31224689	93676	0	0
NpSampleCntCfg_M	31224689	31138496	0	0

LpSampleCntCfg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	31138496	0	0
T1	66900	66845	0	0
T2	786	722	0	0
T3	99572	99513	0	0
T4	32568	32475	0	0
T5	38082	38021	0	0
T6	90	1	0	0
T7	33623	33542	0	0
T8	33277	33191	0	0
T9	49529	48998	0	0
T10	67855	67755	0	0

NpCntClrMisMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	159633	0	0
T1	66900	696	0	0
T2	786	12	0	0
T3	99572	836	0	0
T4	32568	16	0	0
T5	38082	161	0	0
T6	90	0	0	0
T7	33623	68	0	0
T8	33277	54	0	0
T9	49529	212	0	0
T10	67855	37	0	0
T11	0	25	0	0

NpCntClrPwrDn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	93676	0	0
T1	66900	139	0	0
T2	786	85	0	0
T3	99572	192	0	0
T4	32568	76	0	0
T5	38082	70	0	0
T6	90	1	0	0
T7	33623	81	0	0
T8	33277	74	0	0
T9	49529	91	0	0
T10	67855	137	0	0

NpSampleCntCfg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	31224689	31138496	0	0
T1	66900	66845	0	0
T2	786	722	0	0
T3	99572	99513	0	0
T4	32568	32475	0	0
T5	38082	38021	0	0
T6	90	1	0	0
T7	33623	33542	0	0
T8	33277	33191	0	0
T9	49529	48998	0	0
T10	67855	67755	0	0